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    題名: New architecture for high throughput-rate real-time 2-D DCT and the VLSI design
    作者: Chiang, Jen-shiun;Huang, Hsiang-chou
    貢獻者: 淡江大學電機工程學系
    日期: 1996-09-23
    上傳時間: 2010-04-15 10:57:06 (UTC+8)
    出版者: N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
    摘要: The discrete cosine transform (DCT) has been widely used as the core of digital image and video signal compression. However, its computation is so intensive and is of great necessity to meet the requirement of high speed. In this paper, a new architecture for the VLSI design of 2-D DCT has been developed. This architecture contains the following features: (1) using the programmable logic array (PLA) to replace multipliers, (2) overlapped row-column operations and pipeline structure to reduce the total computation time, and (3) highly modular and regular structure for the efficient VLSI implementation. The architecture is implemented to a 8×8 2-D DCT. The circuit is designed by UMC's 0.8 μm spdm CMOS process and the cell library is provided by ITRI CCL. The simulation is shown that the speed of the data processing for this DCT is more than 50 MHz. It performs equivalently 800 million multiplication and accumulations per second
    關聯: ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International, pp.219-222
    DOI: 10.1109/ASIC.1996.551997
    顯示於類別:[電機工程學系暨研究所] 會議論文

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