The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors

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Title:	The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors
Authors:	Chiang, Jen-shiun;Hu, Chih-wei
Contributors:	淡江大學電機工程學系
Date:	1997-06-09
Issue Date:	2010-04-15 11:02:39 (UTC+8)
Publisher:	N.Y.: Institute of Electrical and Electronic Engineers (IEEE)
Abstract:	The performance of a delta-sigma modulator (Δ ΣM) is degraded due to the low op-amp gain, the clock feedthrough noise, and the right or fault of charge transferring between capacitors. Hurst et al. in 1993 suggested an architecture which uses reduced sensitivity to the op-amp gain. Since the low op-amp gain is much easier to design and makes the design of a Δ ΣM become very easy. However, they do not overcome the noise effect of the Δ ΣM. Here, another design is proposed and the effect of noise is reduced
Relation:	Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol.3, pp.2016-2019
DOI:	10.1109/ISCAS.1997.621550
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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