淡江大學機構典藏:Item 987654321/38557
English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 62797/95867 (66%)
造訪人次 : 3738234      線上人數 : 360
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/38557


    題名: A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique
    作者: 江正雄;Chiang, Jen-shiun;Chou, Pao-chu
    貢獻者: 淡江大學電機工程學系
    日期: 1998-11-24
    上傳時間: 2010-04-15 10:46:30 (UTC+8)
    出版者: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity to the gain of operating amplifier. In the low voltage high order ΣΔ modulator, the gain of the operating amplifier is usually the most critical problem of the design. In order to overcome the difficulties of the high gain low voltage operating amplifier, we try to use medium gain operating amplifiers to design a fourth order multistage ΣΔ modulator, and find that it functions very well. The modulator is realized in a 0.5 μm DPDM process with an active area of 1.8 mm2. The HSPICE simulation shows this ΣΔ modulator with a maximum signal-to-noise-ratio (SNR) of 91 dB.
    關聯: Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on, pp.1-4
    DOI: 10.1109/APCCAS.1998.743643
    顯示於類別:[電機工程學系暨研究所] 會議論文

    文件中的檔案:

    檔案 描述 大小格式瀏覽次數
    0780351460_p1-4.pdf383KbAdobe PDF674檢視/開啟
    index.html0KbHTML261檢視/開啟

    在機構典藏中所有的資料項目都受到原著作權保護.

    TAIR相關文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋