A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique

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题名:	A 3.3 V two-stage fourth-order sigma-delta modulator with gain compensation technique
作者:	江正雄;Chiang, Jen-shiun;Chou, Pao-chu
贡献者:	淡江大學電機工程學系
日期:	1998-11-24
上传时间:	2010-04-15 10:46:30 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	We propose a multistage fourth order sigma-delta (ΣΔ) modulator with reduced sensitivity to the gain of operating amplifier. In the low voltage high order ΣΔ modulator, the gain of the operating amplifier is usually the most critical problem of the design. In order to overcome the difficulties of the high gain low voltage operating amplifier, we try to use medium gain operating amplifiers to design a fourth order multistage ΣΔ modulator, and find that it functions very well. The modulator is realized in a 0.5 μm DPDM process with an active area of 1.8 mm2. The HSPICE simulation shows this ΣΔ modulator with a maximum signal-to-noise-ratio (SNR) of 91 dB.
關聯:	Circuits and Systems, 1998. IEEE APCCAS 1998. The 1998 IEEE Asia-Pacific Conference on, pp.1-4
DOI:	10.1109/APCCAS.1998.743643
显示于类别:	[電機工程學系暨研究所] 會議論文

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