A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/38553

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題名:	A 3.3 V all digital phase-locked loop with small DCO hardware and fast phase lock
作者:	江正雄;Chiang, Jen-shiun;Chen, Kuang-yuan
貢獻者:	淡江大學電機工程學系
日期:	1998-05-31
上傳時間:	2010-04-15 10:55:00 (UTC+8)
出版者:	Institute of Electrical and Electronics Engineers (IEEE)
摘要:	In this paper, we aim to design and implement an all digital phase-locked loop (ADPLL) circuit. The core of the ADPLL is the switch-tuning digital control oscillator (DCO). Our design of the DCO has features of small hardware cost. This ADPLL has characteristics of fast frequency locking, full digitization, easy design and implementation, and good stability. It is suitable to be used as the clock generator for high performance microprocessors. A prototype of this ADPLL chip is designed and implemented by TSMC's 0.6 μm SPDM CMOS process. The simulation shows that this chip can operate in the range between 60 MHz and 400 MHz, and operates at 4× the reference clock frequency. The phase lock process is 47 clock cycles, and the phase error is less than 0.1 ns. The IC consists of 4026 MOS transistors and the core size of the chip layout is 923 μm×921 μm.
關聯:	Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on (Volume:3 ), pp.554-557
DOI:	10.1109/ISCAS.1998.704072
顯示於類別:	[電機工程學系暨研究所] 會議論文

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