An efficient VLSI architecture for RSA public-key cryptosystem

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Title:	An efficient VLSI architecture for RSA public-key cryptosystem
Other Titles:	具高效能RSA公開金匙編碼系統之超大型積體電路架構
Authors:	江正雄;Chiang, Jen-shiun;Chen, Jian-kao
Contributors:	淡江大學電機工程學系
Date:	1999-07
Issue Date:	2010-04-15 10:47:23 (UTC+8)
Publisher:	Institute of Electrical and Electronics Engineers (IEEE)
Abstract:	In this paper, a new efficient VLSI architecture to compute RSA public-key cryptosystem is proposed. The modified H-algorithm is applied to find the modular exponentiation. By this modified H-algorithm, the modular multiplication steps were reduced by about 5n/18. For the modular multiplication the L-algorithm (LSB first) is used. In the architecture of the modular multiplication the iteration times are only half of Montgomery's algorithm and the H-algorithm. By this arrangement, this architecture of RSA has a very good area-time product.
Relation:	Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on (Volume:1 ), pp.496-499
DOI:	10.1109/ISCAS.1999.777936
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Proceeding

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