Institute of Electrical and Electronics Engineers (IEEE)
The "Bryn Processor" is a well-known array processor; its design depends on spectral densities of the signal and noise processes. Array output signal-to-noise ratio can be decreased because of errors in sampling times: (1) When array design parameters are estimated from sampled data; (2) when operating on sampled input data. We model errors in sampling times as a discrete-parameter random process. Expressions for array output SNR of the Bryn processor are determined for the two situations listed above. Numerical results are presented for some specific assumptions on signal, noise, and sampling error.
ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing 3, pp.143-147