| Abstract: | 在現代行動通訊及無線網路系統的應用上，類比/數位轉換器(A/D Converter)在其系統中扮演極其重要的角色。超取樣和雜訊移頻技術則是早已被應用於現代超大型積體電路中的類比數位轉換介面，由於超取樣的特性，使得三角積分調變器通常都被限制在音頻信號的應用上。而隨著超大型積體電路製程的改良，使許多的研究逐漸轉移到寬頻帶的應用上，如802.11a、xDSL、Bluetooth、GSM及WCDMA等。
在現代行動通訊及網路系統對高頻寬的需求下，一般傳統的低階三角積分調變器已經無法勝任這高頻寬的需求，所以高階且多位元的三角積分調變器在高頻寬系統上是必須的。而產品未來的發展導向將朝向體積小巧、價格低廉、及較長的待機時間發展，因此SOC(System-on-Chip)及低功率消耗的設計概念將是未來無線寬頻及行動通訊技術發展的不可或缺的兩個要素。
本論文所研究的方向為設計並實現適用於GSM及WCDMA的雙頻帶三角積分器及適用於802.11a系統下之寬頻低功率三角積分調變器。在設計考量上由於類比電路中的積分器會產生許多非理想的誤差，如有限的直流增益,電容偏差...等等，這些電路上的非理想誤差會對我們的高階三角積分調變器造成很大的影響，在本論文中我們將這些非理想的誤差用Matlab及Simulink這兩套軟體來將其加入我們的模型中,以期達到更精準的高階三角積分調變器性能。而且由於我們可以由此模型訂出我們最佳化的係數及電路規格，這樣便可以大大的節省設計的時間。而且在電路實現時也會有設計的準則及目標。
本篇論文所提出之應用於GSM及WCDMA的雙頻帶三角積分調變器，已在0.18微米1P6M標準製程中實現，工作電壓為1.8V，GSM及WCDMA的寬頻分別為200KHz及2MHz，取樣頻率為32MHz，超取樣比為80及8，量測結果顯示其動態輸入範圍為76及68dB，在WCDMA模式下功率消耗為28mW。另一個應用於802.11a系統下之寬頻低功率三角積分調變器，將在0.18微米1P6M標準製程加以設計實現，工作電壓為1.8V，寬頻為10MHz，取樣頻率為160MHz，超取樣比為8，模擬結果顯示在取樣頻率160MHz下其動態輸入範圍為74dB，而最大的訊號雜訊失真比為70dB，總功率消耗38mW。
In the applications for the modern communication and wireless network systems, the analog-to-digital (A/D) converters play an important role in the systems. The over-sampling and noise shaping techniques are used in analog to digital conversion interface of modern very-large-scaled integrated circuits. Due to over-sampling characteristics, the delta sigma (ΔΣ) modulators usually are limited on the application of voice band signals. As the integrated circuits process improvement, it makes many researches transfer to applications of wide-bandwidth gradually, such as 802.11a, xDSL, Bluetooth, GSM, and WCDMA.
Analog-to-digital converters based on the delta ΔΣ modulators have become popular in various applications. Due to the wide bandwidth requirement of modern communication and network, however, the low-order single-bit ΔΣ modulator cannot suit in wide bandwidth applications. Therefore, the high-order multi-bit ΔΣ modulator is necessary in wide bandwidth applications. With the improvement of the VLSI technique, all of these modules are expected to integrate for less chip area, low cost, and low power consumption. Therefore, the SOC (System on a Chip) and low power consumption are the most important concepts in the development for the modern communication and network systems.
In this thesis, we want to design wideband, lower power delta sigma modulator for WCDMA and GSM dual bandwidth and 802.11a applications. Furthermore, the circuit non-idealities effects also can be included in our architectures to predict the final performance of actual the ΔΣ modulators. According to these non-idealities models and analyses, we can obtain the optimum circuit specifications to implement our ΔΣ modulators. Therefore, the design cycle time can be reduced effectively and the circuits also can be implemented based on these optimum specifications.
In this thesis, a wideband, lower power ΔΣ modulator for W-CDMA and GSM dual bandwidth application is implemented in a standard 0.18-μm 1P6M CMOS technology. For the W-CDMA applications, the measurements indicate a dynamic range of 68dB and a SNDR of 61dB. For the GSM applications, the measurements indicate a dynamic range of 76dB and a SNDR of 70dB. The core area is 0.84mm2, and the power consumption is 28-mW at 1.8V. Another lower power ΔΣ modulator in applications of 802.11a is implemented in a standard 0.18-μm 1P6M CMOS technology, too. The simulation results show that the bandwidth is 10MHz；the sampling frequency is 160MHz；the dynamic range and the peak signal to noise ratio are 74dB and 70 dB respectively, and the total power dissipation is 38-mW at 1.8V. |
