在本篇論文中，我們提出一個依照傳統的LBIST Controller架構，所修改的最新的架構，它可以降低測試應用時間(test application time)以及測試功率的消耗。我們使用ATPG產生的測試向量，此測試向量包含未確定的位元(unspecified bit)，此位元可以填入0或1。經過我們提出的演算法後，我們會將測試向量分成數個測試組合排程(section schemes)，演算法的部分我們會在第三章節詳述。然後將此結果對應至我們提出的硬體架構，當Section Counter數值大於零的時候，掃描電路會縮短長度，測試向量直接經由多工器跳過不需要輸入測試向量的掃描電路，此時這些掃描電路的數值是不變的，我們稱為固定的掃描電路(Fixed Group)，硬體架構的部分我們會在第二章節詳述。因為測試元件(scan cell)的數值是不變的，因此也沒有功率消耗的問題，因此我們提出的架構可以節省功率消耗以及測試應用時間。我們使用ISCAS’89 benchmarks來模擬我們的結果，整體來說，節省了大約20%~60%的測試功率消耗以及50%~80%的測試應用時間，詳細的模擬結果會在最後一個章節詳述。 Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the responses are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value.
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may use longer test time and more power consumption, then it would not provide sufficiently high fault coverage and many patterns were undetected faults (useless patterns). In order to reduce the test time and power consumption in testing, we modify the scan chain architecture and use critical patterns from ATPG to improve test length and achieve high fault coverage.
In this paper, we proposed a novel hardware architecture base on “LBIST Controller” to reduce test application time and test power consumption. A given test cubes with unspecified bits that generated by a sequential automatic test pattern generator (ATPG). Using the proposed algorithm in chapter 4.3 can group test cubes to several section schemes, then mapping to the proposed hardware architecture in chapter 4.1 and chapter 4.2. While “Section Counter” is more than zero, scan in could go through MUX and bypass the flip-flops in “Fixed Group”. And we can save power consumption and test application time. According to our simulation results, we reduce about 20%~60% power consumption and 50%~80% test application time in some ISCAS’89 benchmarks.