隨著可攜式電子產品市場的快速成長，以及人們對於產品輕薄短小和電池的長時效性要求，發展低電流、低功耗的積體電路技術有愈來愈急迫的需要。然而，若藉由供應電壓的下降，雖可有效地節省數位電路的消耗功率，但反而會增加高解析度類比電路設計的困難。因此，如何同時將類比至數位轉換器(Analog-to-Digital Converter)的消耗功率大幅減少，並維持效能不變，這對於混合信號電路的設計者來說是一項很大的挑戰。 由於三角積分調變器(Delta-Sigma Modulator)具有較佳的線性度以及對電路元件變異較不敏感，非常適合用來實現高解析度、高精確度的類比數位轉換器，也因此在音頻及通訊領域有相當多的應用。然而，傳統的三角積分調變器多半需要使用到運算放大器，加上若要使調變器能有足夠好的效能，對系統架構的要求往往在二階以上。雖然雙取樣(Double Sampling)技術可減少運算放大器的使用並降低對運算放大器規格上的要求，同時卻也因為雙取樣電路的關係，對於電路元件的需求增加了一倍。也就是說，雖然省去了運算放大器的功率消耗，但其他電路元件的功率消耗卻增加了。因此，對於傳統二階以上架構或是雙取樣的電路實現方式，較大的消耗功率都是在所難免。 近年的文獻中，新近發展出來的電荷傳輸放大器(Charge-Transfer Amplifier, CTA)技術，最大特點在於其幾近為零的靜態功率消耗。因此，電荷傳輸放大器將能更有效地大幅降低電路之消耗功率。若要發展低功耗的積體電路，利用電荷此技術來實現將會是一可行的辦法。本論文提出不使用運算放大器來實現三角積分調變器的全新技術，並藉由成功發展出全差動式電荷傳輸放大器(FDCTA)以及全差動式電荷傳輸積分器(FDCTI)，實現了此構想。當頻寬為4 kHz，取樣頻率為2.5 MHz時，此調變器之訊號雜訊比(SNR)可達67 dB，解析度達11 bits。當供應電壓為1.8 V時，類比部份的功耗為3.4 μW，總功耗為36 μW。 With rapid growth of the market in the portable electronic products, there is a strong demand for developing less current and low power consumption circuit technique to increase the system level integration density and prolong the battery lifetime. However, the reduced supply voltage results in the power saving in digital circuits, but complicates the design of high resolution analog circuits. It is also a great challenge to maintain the desired performance of the analog-to-digital converters (ADCs) while the power consumption is greatly reduced. Since delta-sigma (ΔΣ) modulators have better linearity and insensitivity to device variation, they are well suitable for the realization of high-resolution and high-accuracy A/D converters in audio and communications applications. However, it is usually required to design a high-order ΔΣ modulator with the power-hungry opamps to satisfy the specific performance. In some state-of-the-art literatures, double-sampling technique is often used to reduce the performance requirement of opamp at the cost of double devices. In other words, double-sampling technique reduces the power consumed by opamp, but increases that from additional double devices. Consequently, it is difficult to reduce the power consumption of the ΔΣ modulators with conventional architecture and technique. From the recent literatures, we know that the advantage of the charge-transfer amplifier (CTA) technique is the almost zero static power consumption. Therefore, the CTA technique exhibits a substantial power-saving feature and it will be an attractive method for low-power application. This research proposes a brand-new technique without the use of opamp to realize the delta-sigma (ΔΣ) modulator by developing both the fully-differential charge-transfer amplifier (FDCTA) and integrator (FDCTI). The presented ΔΣ modulator reaches a 67 dB of peak SNR when the bandwidth is 4 kHz, and the sampling rate is 2.5 MHz. The power consumption of the analog part of this modulator is 3.4 μW, and the total power consumption of the whole modulator is 36 μW at a 1.8 V of supply voltage.
