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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/35894

    Title: A third-order multi-bit delta-sigma modulator with mciff structure for wideband applications
    Other Titles: 應用於寬頻之MCIFF架構三階多位元三角積分調變器
    Authors: 陳建宇;Chen, Chien-yu
    Contributors: 淡江大學電機工程學系碩士班
    郭建宏;Kuo, Chien-hung
    Keywords: 三角積分調變器;低失真;分佈式前饋串級積分器;前饋式;Delta-Sigma Modulator;low-distortion;MCIFF;feedforward
    Date: 2009
    Issue Date: 2010-01-11 07:17:17 (UTC+8)
    Abstract: 近幾年來,在通訊應用過程中,由於便攜式電子產品可觀的發展,低功率電路發展已經被深入的研究。面對此目標,藉由先進CMOS技術的繼續發展,很多低電壓和低功率設計被此因素所激勵。雖然如此,但隨著供應電壓的減少,此結果阻礙了應用於寬頻之高解析度、高準確性之低功率類比數位轉換器的發展。
    此論文提出應用於寬頻之三階低失真、多位元之三角積分調變器。修改過之分佈式前饋串級積分器架構再次被改善,在實現上,調變器在量化器前不需要一個加法器,進而節省電源功率消耗,且在此被改善的調變器中,最佳化了放大器的需求電流,使得縮小了總共電流。在此多位元IMCIFF調變器中。此電路原理已經被實現在三階四位元三角積分調變器,且已經於0.18 μm 製程被製作。操作於頻寬200 kHz,使用時脈頻率為13.76 MHz之調變器,模擬之訊號雜訊脈衝比為93.69 dB。操作於電源供應電壓為1.8 V時,此電路之總消耗功率為4.034 mW。
    In recent years, there has been a dramatic proliferation of research concerned with the low-power circuits due to the substantial growth of the portable electronic products in communication applications [1-3]. Toward this aim, many low-voltage and low-power designs have been devoted to with the incitation of the continuing progress of the advanced CMOS technology [4-5]. Nevertheless, the decrease of supply voltage retards the development of the low-power analog-to-digital converters (ADCs) in high-resolution high-accuracy wide-bandwidth applications.
    This thesis presents the improved third-order low-distortion multi-bit delta-sigma modulator for wideband applications. The improvement of modified cascade integrators with distributed feedforward (IMCIFF) structure without summer in front of quantizer is realized to save the power consumption in the presented modulator. We take the optimum current of all Opamps in this improved modulator and make the total current be reduced. The prototype circuit is realized in the third-order multi-bit Delta-sigma (ΔΣ) modulator, which has been fabricated in 0.18μm 1P6M CMOS process. The simulated signal-to-noise plus distortion ratio (SNDR) of the modulator within a 200 kHz of bandwidth under a 13.76 MHz of clock rate is 93.69 dB. The total power consumption of the modulator is 4.034 mW at a 1.8 V of supply voltage.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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