適用於USB 2.0的寬頻操作具有低電壓及抗雜訊之鎖相迴路

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Thesis > Item 987654321/35889

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Title:	適用於USB 2.0的寬頻操作具有低電壓及抗雜訊之鎖相迴路
Other Titles:	A wide-range phase-locked loop with low voltage and noise-immunity for USB 2.0
Authors:	王吉雄;Wang, Chi-hsiung
Contributors:	淡江大學電機工程學系碩士班江正雄;Chiang, Jen-shiun
Keywords:	鎖相迴路;USB 2.0;Phase-Locked Loop;VCO;UTMI
Date:	2009
Issue Date:	2010-01-11 07:16:46 (UTC+8)
Abstract:	近三十幾年來，鎖相迴路(Phase-Locked Loop, PLL)已經被廣泛地應用在各個研究領域中，包括訊號產生器、頻率合成器、訊號與資料復原等等。而鎖相迴路的主要功能在於鎖定相位，並輸出所要的頻率，而目前的應用其速度越來越快，使得晶片內部的相位產生偏差延遲，導致傳輸的資料錯誤。　　對於講求高速傳輸的時代而言，其鎖相迴路的抗雜訊能力要高，在電路中所討論的雜訊不外乎有頻率漂移量(Jitter)、相位誤差(Phase Error)，以及電源供應的雜訊(Power Supply Noise)，且因系統要求的頻率越來越快，所以使得功率消耗變大，因此鎖相迴路的另一話題就是如何降低功率消耗，並且符合現今的電子系統規格。　　本論文主要是針對其電路的功率消耗(使用低電壓)及頻率可用範圍做改善，而本論文因使用切換電流的方式使低電壓鎖相迴路達到寬頻率的應用，且將此寬頻率低電壓的鎖相迴路應用在USB 2.0的系統上。 Nearly 30 years ago, PLL (Phase-Locked Loop, PLL) has been widely used in various research fields, including signal generators, frequency synthesizers, clock and data recovery and so on. The main function of PLL is phase locked. The applications of PLL can make frequency become faster, and make the chip''s internal phase delay bias, leading to transmission of data errors. The emphasis on the era of high-speed transmission, PLL must have high noise immunity. There are some problems in circuits such as Jitter, Phase Error, as well as the Power Supply Noise. Because the requirement of the system frequency becomes faster and faster, power consumption becomes large. PLL is another topic of how to reduce power consumption, and in line with the specifications of today''s electronic systems. This paper is mainly to reduce the power consumption of PLL by using low-voltage and expand the range of frequency. In this paper, switching current is adopted so wide-range PLL with low-voltage can be performed for USB 2.0.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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