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    Title: Design of low voltage low power delta sigma modulators
    Other Titles: 低電壓低功率三角積分調變器之設計
    Authors: 張剛碩;Chang, Kang-shuo
    Contributors: 淡江大學電機工程學系碩士班
    郭建宏;Kuo, Chien-hung
    Keywords: 三角積分調變器;交換式運算放大器;雙取樣;delta sigma modulator;switched-opamp;double sampling
    Date: 2006
    Issue Date: 2010-01-11 07:14:21 (UTC+8)
    Abstract: 近年來對於可攜式電子裝置需求日益增高,相關產品如雨後春筍般被上市,此類產品由於講究可以隨身攜帶,因此對於省電要求也相對提高。為了因應此需求,低電壓低功率產品已經陸續被開發出來。低電壓低功率已經為現在之趨勢,預估未來2010年時,CMOS電路供應電壓可下降至0.7V[32]。隨著製成的推進電壓之下降可以達到更高頻率以及更低之消耗功率。雖然電壓之下降對數位電路有上述之優勢,但是類比電路會比預期來的難以設計,要維持與高電壓相匹配之性能,勢必為一大挑戰。

    在現今晶片應用當中,類比數位轉換器為一系統之重要部份。其目標為到達高解析度以及低功率,其常見實現的架構眾多,包括快閃式數位類比轉換器(Flash A/D)、管線式類比數位轉換器(Pipeline A/D)、三角積分調變器(Delta sigma modulator)等。其中各有其優劣,然而要到應用於高解析度(16-bit)音頻(Audio)應用的話,三角積分調變器是非常適合去完成的。由於它對無論是運算放大器之增益或電路之間的誤差相對較不敏感,這些特性應用於低電壓電路十分合適,因此本論文使用三角積分調變器來達成低電壓之設計。
    本論文提出兩種架構之低電壓調變器,第一種是建立於低雜訊架構之多級串疊架構,此架構有較低之輸出擺幅以及較大之動態範圍(DR),非常適合在低電下下操作。每級分別提供二階雜訊移頻,總共可提供四階雜訊移頻而沒有穩定度問題。模擬結果最大的訊號雜訊比可達到89dB,在1V的供應電壓下,消耗功率只有900微瓦,取樣頻率為4MHz。另一架構為低電壓多位元調變器,本論文提出新架構之數位類比轉換(DAC)回授,用來克服開關浮接的問題,在1V的供應電壓下,消耗功率為1.8毫瓦,時脈頻率為2.5MHz,量測結果最大訊號雜訊比為80dB。
    The trend towards low voltage, low power, portable audio products has been growing quickly. There is a deep desire to develop low power and low voltage circuitries. Today the 90nm generation uses 1.2V supply voltage and it will be scaled down to under 0.7V for 2010[32]. The supply voltage will be decreased when CMOS process scales down, and furthermore it could be achieved low power, low cost and high speed systems.
    There are some structures to implement ADCs, such as pipeline ADC, flash ADC, etc. In high resolution application, the switched-capacitor (SC) technique is the most popular approach for implementing ADCs due to the precise ratio on the integrated capacitors. Especially the delta sigma modulator is suitable to realize a high resolution application. Due to delta sigma modulators are insensitive on analog components such as opamp and comparator. The requirement of oversampling converter can be relaxed. It not only achieves high resolution more easily but also reduces the power dissipation. However, the supply voltage is descending with the scaling technologies. It is a great challenge to design a desired performance when the supply voltage is reduced.
    The aim of this thesis is to design a low-power and low-voltage delta sigma modulator. There are two works in this thesis. First, a 1V 2-2 MASH delta sigma modulator is based on low distortion structure. The simulated total power dissipation is only 0.9mW. The peak SNDR of the modulator is 89dB within a bandwidth of 22.05kHz. Second, a 1V multibit delta sigma modulator using a single-opamp is proposed. The peak SNDR of the second-order modulator is 82dB within a bandwidth of 22.05kHz. The measured total power dissipation is 1.8mW.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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