本篇論文主要是在描述運用在0.18μm CMOS制程下，設計ㄧ個應用於音頻之極低電壓多位元三角積分調變器。本篇應用於雙取樣技術，始時脈可以被更有效的運用，並減輕運算放大器在設計上的困難。在本篇論文中我們也設計的一個新的低電壓多位元比較器，有別於傳統的電阻分壓法，減少不必要的靜態功率的消耗。 應用於音頻之極低電壓多位元三角積分調變器所達到的SNDR為88dB，而他的動態範圍為89dB，當基頻為22.05KHz，輸入頻率為88dB，而他的動態範圍為89dB，輸入頻率為1.25KHz。當供應電壓為0.8V時，所消耗的能量為4.2mW。 This paper presents a 0.8 V multibit delta-sigma (ΔΣ) modulator with a single switched-opamp (SOP) in a 0.18 μm 1P6M CMOS technology. The double-sampling technique is adopted in the modulator to promote the clock efficiency and relax the requirement of SOP. To improve the accuracy of the multibit quantizer in a low-voltage circumstance and reduce the static power, a new switched-capacitor (SC) multibit quantizer without R-string is proposed. The presented ΔΣ modulator achieves a signal-to-noise-plus-distortion ratio (SNDR) of 88 dB and dynamic range (DR) of 89 dB within a 22 kHz of bandwidth under a 1.25MHz of clock rate. The power consumption of the presented modulator is 4.2 mW at a 0.8 V of supply voltage.
