隨著積體電路的製程技術不斷的演進，截至目前業已進入了奈米製程。然而在類比電路的設計與實現上卻沒有明顯受益，肇因於臨界電壓並未顯著減少。而製程的不斷演進，閘極的崩潰電壓持續降低，所以電源電壓也需要相對地減少。因此低電壓電路技術的發展有愈來愈急迫的需要。且低電壓電路技術能更有效地縮小電池的體積及重量，而這才符合可攜式個人無線電子通信產品之輕薄短小和電池等長時效性等要求。 因為製程的進步與架構的更新，所以寬頻上之應用也愈來愈多。而本篇論文所研究應用的頻寬則是設計並且實現應用於對稱性數位用戶專線(Asymmetric Digital Subscribe Line，ADSL)。 ADSL是現時一般社會大眾所廣泛運用的網路連線方式，目前全球ADSL用戶數量仍在迅速成長，為了刺激ADSL的持續成長，市場需要低成本、高效能的ADSL積體電路，就成本來考量ADSL，若能將各種元件整合在一起便是類比前端（Analog Front End，AFE）成功的關鍵，也就是所謂SOC的概念(System on Chip)。數位電路的製程會因為製程的進展而改善，然而類比電路的設計卻因為諸多的因素無法隨著製程演進而有相對大幅度的改良。而在本論文中則研究與設計能夠在低電壓中仍能正常運作之類比數位轉換器，以利於能夠與數位電路更密切的整合。 本論文提出之低電壓寬頻三角積分調變器，是運用二種架構所組成之多級串疊架構。第一級的架構是運用低雜訊架構，而第二級則是傳統之多級回授架構。而每級分別能提供兩階的雜訊移頻，所以整體系統能夠提供四階的雜訊移頻。且採用了雙取樣技術以增進時脈效益並紓緩運算放大器之規格需求。而所提出之調變器已於0.13微米1P8M標準製程實現，於ADSL之應用頻寬1.1 MHz下，時脈頻率為20MHz，其最大之訊號雜訊比可達到 79.390 dB 動態範圍更可達到 82.103 dB。而在僅只0.8伏特之供應電壓之下，整體的消耗功率只有15.7毫瓦。 With the improvement of the process of the integrated circuit, nanometer technology is applied. However it is not benefited greatly to design and implement the analog circuit due to the threshold voltage is less decreased. Due to the improvement of the process, the power supply has to decrease in proportion to the breakdown voltage of the gate. The requirement of the low voltage circuit design is getting bigger and bigger. The low voltage circuit design can effectively reduce the volume and weight of the battery. It satisfies the portability and the battery life of the portable wireless communications products. The improvement of the process and architecture, the wideband applications grow up greatly. ADSL is one of the most popular methods of the internet connection. The number of the ADSL users is increasing quickly. In order to improve the development of ADSL, low cost and high performance IC is required. In mention of the cost, the key point to implement an efficient AFE is how to integrate each element effectively. It is the concept of SOC. Digital IC get advance due to the process improvement, but analog IC do not. In this thesis, we discuss and design the ADC work in low supply voltage to integrate with the digital integrated circuit more compactly. We present a low voltage wideband delta-sigma modulator. The MASH architecture is combined with two structures. The first stage is low distortion structure and the second stage is traditional feedback one. Each stage performs second-order noise shaping, and the entire system can accomplish fourth-order noise shaping. Double sampling is used to promote the clock efficiency and relax the requirement of the opamps. The proposed modulator has been implemented in a 0.13
