English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 51258/86283 (59%)
造訪人次 : 8013462      線上人數 : 63
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/35801


    題名: UART介面的記憶體架構平台設計
    其他題名: Design of memory architecture with UART
    作者: 賴俊鳴;Lai, Chun-ming
    貢獻者: 淡江大學電機工程學系碩士班
    簡丞志;Chien, Cheng-chih;周永山;Chou, Yung-shan
    關鍵詞: 快閃記憶體;Flash Memory;UART;FPGA;Storage
    日期: 2005
    上傳時間: 2010-01-11 07:10:52 (UTC+8)
    摘要: 目前手持式或是嵌入式電子產品的市場趨向以慢慢趨向複合性多功能,雖然功能上的需求越來越多,但產品價格卻相對的必須越來越低才能具市場競爭力。在這些產品裡佔有較高需求與高成本的零件當屬記憶體;從早期的以SRAM和Nor Flash為主;漸漸進步為SRAM+ Nor Flash+ NAND Flash再慢慢變成為以NAND Flash和DRAM為主幹。
    本論文的研究目的在於發展低成本與簡易介面構成之記憶體架構,以方便未來不要求高速與影像處理的電子產品可以MCU〈如8051之micro-controller〉來進行產品開發。
    為能應用在一般的MCU 8-bits micro-controller上,因此考量以串列的介面為主,即UART為介面傳輸;並以此介面結合低價的NAND Flash,以構成所需之大容量記憶體架構。而應用此UART的優點為未來只需加強UART的傳輸速率即可達成高速存取的目的。
    本論文目的的實現主要將使用8051 MCU、Altera FPGA、及NAND Flash快閃記憶體三種主要元件所組成的單元來完成硬體平台架構設計,並利用實體驗證的結果來引證本文所提出之記憶體架構及使用之UART介面是否可行。
    The market of the handheld device or the embedded electronic product trend are compounding function at present, and needs functions more and more, product cost has been trending down to have market competitiveness . Occupy than the high demand in these products and the expensive part is storage devices. From rely mainly on SRAM and Nor Flash early; it is become for SRAM+ NAND Flash+ Nor Flash, to progress gradually for as the backbone with NAND Flash and DRAM.
    The research purpose of this paper in developing storage device architecture that cost-efficient and simple and easy interface form, the storage devices can be used in MCU and that do not require high speed performance and high video performance when we develop electronic product.
    In order to apply it to general MCU 8bits micro-controller , so consider the interface that transfer must used easy and usually, like UART. And combine NAND Flash of the low price with this interface, in order to form necessary large capacity storage device architecture. And if we want to upgrade the transfer rate in the future, we just upgrade the baud-rate in UART.
    The realization of this paper purpose will use 8051 MCU , Altera FPGA, and NAND Flash to carry out the platform design of the hardware, and it is feasible to make use of result that the entity proves to quote storing device structure with UART interface used that this paper put forward as proof.
    顯示於類別:[電機工程學系暨研究所] 學位論文

    文件中的檔案:

    檔案 大小格式瀏覽次數
    0KbUnknown529檢視/開啟

    在機構典藏中所有的資料項目都受到原著作權保護.

    TAIR相關文章

    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋