在本論文中，我們研究超低功率與超低工作電流無線傳輸系統之模擬設計，使用200KHz之sample time，超低頻之40KHz載波，輸出信號為一2.5us之脈波信號，最後利用這脈波信號當成載波來傳送資訊，因此會非常的節省功率的消秏，最後以Verilog硬體描述語言撰寫一超低功率無線傳輸系統，使用ModelSim模擬軟體驗證，最後將實現於FPGA發展平台上。 最後的干擾模擬結果，可以發現在35kHz以下與50kHz以上之干擾，均能被此系統濾除。 In this thesis, we study the simulation design of a wireless transmission system with ultra low power and ultra low operating current. We generate an output pulse signal with a pulse width of 2.5 us through the utilization of 200 KHz timing pulses and data transmitting at ultra low rate 40 KHz. This pulse signal is then employed as a carrier signal to convey information so as to extremely save the system power consumption. We finally utilize Verilog hardware description (HDL) language to design a wireless transmission system with ultra low power consumption, and exploit ModelSim software language to verify the design and finally the system hardware is realized on the FPGA developed platform.
