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| Title: | GFSK傳收機系統模擬設計之濾波器最佳化實現 |
| Other Titles: | The filter optimization in the simulation design of GFSK transceiver system |
| Authors: | 溫敏如;Wen, Min-ju |
| Contributors: | 淡江大學電機工程學系碩士班
李揚漢;Lee, Yang-han |
| Keywords: | 高斯頻率鍵移;有限脈衝響應濾波器;無限脈衝響應濾波器;Gaussian Frequency Shift Keying |
| Date: | 2007 |
| Issue Date: | 2010-01-11 07:09:34 (UTC+8) |
| Abstract: | 在本篇論文中，我們將探討根據系統規範之高斯頻率鍵移(Gaussian Frequency Shift Keying, GFSK)傳收機系統，利用 “Simulink”模擬軟體建構出GFSK傳收機系統，並設計出符合系統所使用之數位濾波器規格，並藉由模擬結果找出最佳化設計再將數位濾波器於硬體上實現。
論文中，主要在針對GFSK收發機之基頻數位濾波器模擬與設計。首先，對於發射機內的高斯有限脈衝響應(Gaussian Finite Impulse Response, Gaussian FIR)濾波器部分，我們可參照GFSK系統規格的制定，將高斯FIR濾波器之BT設為0.5，並依循此設定找出適當的3-dB頻寬做為高斯FIR濾波器之設計規格。接著在接收機部份，我們設計了兩種濾波器，首先是針對在通道部份的數位帶通濾波器，並採用FIR濾波器，且依規格設計出適用於各種頻率偏差下之最佳化的設計方式，配合“Simulink”的輔助工具將設計出的濾波器使用硬體描述語言(Verilog HDL)將硬體實現。最後於GFSK接收機解碼後，加入資料濾波器將GFSK解碼後所含之高頻信號去除並還原原始信號，論文中採用無限脈衝響應(Infinite Impulse Response, IIR)濾波器，根據系統規格將不同速率的資料經由低通的IIR資料濾波器將傳送信號完整呈現。
依照上述方式，本論文最佳化之結果為：1.將濾波器系統架構共用於不同傳輸速度。2.使用“Simulink”模擬出FIR通道濾波器之最佳化階層數設計。3.將濾波器內所含之係數量化至最佳化之有限字元長度。
In this thesis we will use the simulation software tool ‘Simulink’ and base on the system specifications of the Gaussian Frequency Shift Keying Transceiver System to design GFSK transceiver system. First we develop the digital filter specifications from the system requirements, and then through system simulation to find the optimal digital filter that is finally implemented by hardware realization.
The main task in this thesis is the design and simulation of the basedband digital filter for the GFSK transceiver system. We study the Finite Impulse Response of the Gaussian filter and follow the GFSK specifications to define and find the BT value for the Gaussian Filter, it is set at 0.5, and then from this BT value we look for and evaluate the appropriate 3-dB filter bandwidth, this filter bandwidth is then defined to be our design specification. In the receiver side, we design two types of filters, first we deign a digital bandpass filter that is implemented to filter the channel impulse response and the second filter is the FIR filter. We develop the design criterion to elaborate the filter design so that the resulting filter will be optimized under various frequency deviations. It then uses the design-assist tool, Simulink, to realize and implement the designed filter through the Verilog hardware description language (Verilog HDL). When the GFSK signal is demodulated, it uses the data filter to eliminate the high frequency part of the demodulated GFSK signal to recover the original data. An Infinite Impulse Response (IIR) filter, that is designed to meet the system specifications for various data rates, is adopted as the data filter to perfectly recover the original data.
In summary, from our developed criterion we have designed an optimal filter possessing the following advantage characteristics: the filter has a common architecture that suitable for use for various data rates, the filter order is optimally determined through the Simulink simulation and finally the filter coefficients have been optimally designed and quantized to finite word lengths. |
| Appears in Collections: | [Graduate Institute & Department of Electrical Engineering] Thesis
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