本論文主題在於使用標準互補式金氧半製程，實現一個有雙回授路徑組成之鎖相迴路。論文內容可以兩個部份，第一部份在第二章，其中分別描述鎖相迴路的原理和分析鎖相迴路整個系統。第三章和第四章為第二部份，敘述了鎖相迴路的電路設計、製作及量測。最後，將在第五章裡做總結。 Phase-locked-loops (PLLs) are widely used in wireless data telecommunications, such as wireless local area networks (WLANs), mobile and satellite communications. In these applications, the PLLs are usually used as a clock synthesis block to generate a high-speed internal clock from an external fixed oscillation source.
There is a tight tradeoff between the settling time and the amplitude of the ripple on the VCO control line in the design of phase-locked loops. This tradeoff for phase-locked RF synthesizers limits the performance in terms of the channel switching speed and the magnitude of the reference sidebands that appear at the output.
This paper presents a double PFDs PLL approach with a tunable delay unit to produce a small ripple on the VCO control line as well as a low jitter performance metric. Besides, the proposed architecture also provide another benefit that less settling time is required compared to the architecture with only one PFD.
Section II develops the fundamental principle for the architecture of the proposed phase-locked loop. The circuit design and simulation results of the presented phase-locked loop are shown in Section III and Section IV, respectively. Finally, a conclusion is given in Section V.
