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    Title: 使用邏輯定址快閃記憶體之微型硬碟模組的設計與實現
    Other Titles: The design and implementation of micro disk module by use LBA NAND flash memory
    Authors: 黃仁芳;Huang, Renfang
    Contributors: 淡江大學電機工程學系碩士班
    簡丞志;Chien, Cheng-chih
    Keywords: 微型硬碟模組;固態硬碟;快閃記憶體;Micro Disk Module;SSD;Flash Memory;ECC
    Date: 2008
    Issue Date: 2010-01-11 07:05:05 (UTC+8)
    Abstract: 本研究目標在於避免智慧型ATA介面控制器在快閃記憶體製程或架構更新時,需重新修正控制器內部對快閃記憶體的錯誤修正能力和記憶體位址管理方式,希望利用新增加的邏輯定址快閃記憶體內含控制器來計算其錯誤校正碼和管理快閃記憶體內部資料位址,以避免智慧型控制器須跟隨著新型快閃記憶體,而改變其內部機制。
    目前固態硬碟(Solid State Disk)的主要系統架構是由一顆智慧型ATA介面控制器和快閃記憶體(Flash Memory)所組成。此智慧型控制器主要是規劃快閃記憶體的管理方式及將資料存取方式轉換成一般ATA介面的存取方式。而快閃記憶體會隨著製程的演進,其所需的錯誤校正碼(Error Correcting Code)會跟著增加,造成智慧型控制器內的錯誤校正機制也必須改變以符合新型的快閃記憶體。
    NAND型快閃記憶體內部結構是以分頁(Page)和區塊(Block)為單位。當快閃記憶體製程改進時,其分頁的容量也會跟著增加,每一分頁所需要的錯誤校正碼會比舊製程來的多。因此本論文採用邏輯定址快閃記憶體,邏輯定址快閃記憶體內含一顆控制器,此顆控制器將原本規劃在智慧型控制器裡的快閃記憶體校正機制提出來,獨立成另一顆Flash控制器,用於檢查其所連接之快閃記憶體的錯誤校正碼。另外此FLASH控制器也將把快閃記憶體以分頁存取的方式轉換成邏輯區塊定址(Logical block address)方式存取,以方便後端ATA智慧型控制器管理。改進後的固態硬碟系統架構將比原本系統架構多增加一顆Flash控制器,此控制器用來規劃與管理快閃記憶體。而原本ATA智慧型控制器將負責本機端(Host)介面的傳輸,且因對快閃記憶體的存取方式改為邏輯區塊定址,在存取資料時的效能上會勝過以分頁存取方式。
    未來的研究方向在於改善快閃記憶體錯誤修正能力及管理方式以提升其可靠度與存取速度,並降低Flash控制器的運算複雜度,進而提升總體固態硬碟效能。
    This research aim to prevent the intellectual ATA interface controller re-correcting flash memory error correcting code and Flash memory address administration from the internal controller, hope to utilize new placed LBA NAND Flash Memory include controller to calculate the error correcting code and administrating the internal information address of the flash memory, preventing intellectual controller being forced to change the internal mechanism by new type of flash memory.
    The combination of current Solid State Disk main system contracture is build by a single intellectual ATA interface controller and Flash Memory. This intellectual controller is aim to program the functionality of flash memory and transforming data access into a general ATA interface access. Error correcting code rose from the Flash Memory processive production process, Force the intellectual controller error correcting mechanism to change to match the new type of the flash memory.
    The unit of the NAND type flash memory internal contracture is divided by page and block. The capacity of the page rose when flash memory production process improves, and the error correcting code in each page becomes more than in the old production process. The meaning of this thesis is using LBA NAND Flash Memory. The LBA NAND Flash Memory include a controller, which tend to propose the flash memory correcting mechanism in original program in the intellectual controller, apply the inspection on the connected flash memory error correcting code. Additionally, this flash controller is functionally transforming the page access into Logical block address access, in advance to administrate by ATA intellectual controller at the back end. After improving the SSD system contracture gains one more flash controller than the original system contracture, this controller is tend to program and administrate the flash memory. The original ATA intellectual controller in respond to charge the host interface transmission, and change the flash memory access into Logical block address, to reduce the data access time with better performance than the way of page access.
    The focus of oncoming research will be on improving the flash memory error correcting capability and administration method in advantage to elevate the reliability and speed, and to reduce the complicity algorithm of Flash controller, for better performance of SSD overall.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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