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    題名: The design of receiver front-end circuits for optical communications
    其他題名: 光通訊接收器前端電路之設計
    作者: 陳之皓;Chen, Chih-hao
    貢獻者: 淡江大學電機工程學系碩士班
    江正雄;Chiang, Jen-shiun
    關鍵詞: 轉阻放大器;限制放大器;光接收器;Transimpedance amplifier;limiting amplifier;optical receiver
    日期: 2007
    上傳時間: 2010-01-11 07:04:36 (UTC+8)
    摘要: 隨著多媒體資訊傳播時代的來臨,網際網路越來越普及,使用端對網路骨幹之資料擷取趨於頻繁,對網路頻寬之需求亦日益增加。由於光訊號具有頻寬高、不受電磁波干擾、低傳輸損失及系統可靠度高等的特性,光纖網路因此兼具寬頻及低損耗之優勢,再加上光電元件的技術日益成熟,光纖網路為當今公認寬頻傳輸之最佳媒介與未來網際網路骨幹之主流。此網路是以雷射二極體或發光二極體,經由光纖,將聲音、影像、或數據資料由發射端發送至接收端,接收端則是由光偵測器及其他相關電路所組成的,其傳收速率可達10 Gb/s。因此光纖通訊的未來極具潛力,值得加以研究及發展。另外,值得一提的是,即使已經有許多光纖接收器是使用較昂貴的特殊製程,例如GaAs,來實現,但由於現今製程技術的進步,使用CMOS製程來實現也是相當普遍的了。本論文的目標即是以TSMC 0.18-μm CMOS製程來完成一操作於1.8 V、 10 Gb/s的光通訊接收器前端電路,其中包含轉阻放大器(Transimpedance Amplifier)與限制放大器(Limiting Amplifier)。
    本論文為應用在光纖通訊系統接收器之研究,主要為一般光纖通訊接收器類比前端電路常用的原理,包括開迴路(共閘極)轉阻放大器與利用主動回授架構設計之限制放大器的研究,其主要目標為製作一低功率、高傳輸速率及高頻寬的接收器類比前端電路。整體系統要求參考同步光纖網路(Synchronous Optical Network, SONET),符合SONET OC-192的規範(即10 Gb/s之資料速率)。為了在節省面積的條件下達到增加頻寬的目的,電路廣泛使用CMOS所組成的主動元件來取代大面積的被動元件如電感、電阻及電容。
    轉阻放大器部份,因為光二極體的寄生電容會降低頻寬,所以我們設法降低輸入所看到的電阻值,因此我們使用了共閘極的輸入級之轉阻放大器。另外,為了額外降低輸入阻值,我們在輸入端加了Regulated Cascode架構的電路。頻寬方面,我們使用了主動電感來增加頻寬,並且在增益級使用了交叉式主動回授(Itersecting Active Feedback)架構來額外增加頻寬。在1.8 V的操作電壓下,轉阻放大器提供了56 dBΩ的轉阻增益及8.27 GHz的-3dB頻寬。
    限制放大器方面,為了達到目標的頻寬,我們使用了三階主動回授的架構來提高頻寬,並用交錯式主動回授(Interleaving Active Feedback)的方式來維持平坦增益。在1.8 V的操作電壓下,限制放大器提供了44.5 dB的差動電壓增益及10.3 GHz的-3dB頻寬。
    With the advent of multimedia age, the internet is more and more popular. And with the growth of the number of internet users, the demanded volume of data transported over the internet backbone has increased. Thanks to that the light signal has the characteristics such as wide bandwidth, immunity against electromagnetic interference, low transmission loss, and high security, the fiber optics have the advantages including low loss and high bandwidth. With the increasing maturity of the technology of photoelectric devices, optical fiber has been acknowledged as the most appropriate medium for wideband transmission and a trend for internet backbone in the future. In fiber optics, The receiver end is made by a photo detector and the corresponding receiver circuits. The highest bit rate of fiber optics can reach 10 Gb/s. Therefore, the fiber optics has great potential in the future and is worth researching and developing. Furthermore, it is worth mentioning that conventional optical receivers are implemented in expensive process such as GaAs process. Even so, with the blooming progress of nowadays process technology, it is popular to implement transceiver circuits in CMOS process. This thesis presents some circuit techniques for the optical receiver front-end design with TSMC 0.18-μm CMOS process. The goal of this research is to realize a single-chip receiver front end, including a transimpedance amplifier and a limiting amplifier, with a 1.8-V supply for 10-Gb/s applications.
    In this thesis, we do the research of the receiver for the application in fiber optical communication systems. The research mainly contains the concepts of the analog front-end circuits in a general fiber optical receiver, which includes an open-loop (common gate) transimpedance amplifier and a limiting amplifier with active feedback. The major goal is to design a low power, high transmission rate, and high bandwidth analog front-end circuit. The specification of the entire system refers to the Synchronous Optical Network (SONET). All circuits are designed to meet the 10 Gb/s data rate for SONET OC-192 standard. In order to extend the bandwidth and save the size area at the same time, the circuits extensively use the CMOS active devices in place of large passive ones such as inductors, resistors, and capacitors.
    In the part of the transimpedance amplifier, since the parasitic capacitance of the photodiode will reduce the bandwidth, we have to think up a method to lower the input impedance. Thus, a common-gate input stage is used. Besides, in order to further lower the input impedance, we add a Regulated Cascode circuit. In bandwidth, we use the active-inductor peaking technique. Also, we employ the intersecting active feedback in the gain stage to further increase the bandwidth. With a 1.8-V supply, the transimpedance amplifier provides a transimpedance gain of 56 dBΩ with a –3-dB bandwidth of 8.27 GHz.
    For the limiting amplifier, in order to fit the objective bandwidth, we use the third-order gain stages with active feedback. Furthermore, we employ the interleaving active feedback technique to restrain the gain peaking. With a 1.8-V supply, the limiting amplifier provides a differential voltage gain of 44.5 dB with a –3-dB bandwidth of 10.3 GHz.
    顯示於類別:[電機工程學系暨研究所] 學位論文

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