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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/35718


    Title: A novel gated scan-cell scheme for low capture power (lcp) in at-speed testing
    Other Titles: 新式的低捕捉功率掃描單元選擇和快速掃描測試
    Authors: 江明穎;Chiang, Ming-ying
    Contributors: 淡江大學電機工程學系碩士班
    饒建奇;Rau, Jiann-chyi
    Keywords: 時脈閘控;掃描測試;低功率;Clock gating;scan testing;low power
    Date: 2009
    Issue Date: 2010-01-11 07:03:17 (UTC+8)
    Abstract: 最近以來,在掃描測試上實現低功率一直是個挑戰。先前有許多的研究都是著重在降低移動功率,只有少部分的研究有考慮到捕捉功率。在捕捉測試結果時,大量的切換動作會產生電源電壓降,進而導致電路故障與測試良率損失。本篇論文將提出一種新的演算法,並配合時脈閘的技術來閘控部分的掃描元件以防止內部電路產生不必要的切換動作。這些掃描元件都被劃分為若干個群組;對於每一個測試向量而言,在捕捉期間只有一部分的群組會對測試結果做存取的動作。我們所提出方法對於錯誤涵蓋率與測試時間不會造成任何影響,只是會增加一小部分的電路面積。經由ISCAS’89測試電路的實驗結果可知捕捉功率平均可以減少將近40%並且而外的硬體面積大約為5.49%。
    Recently, low power implementation is a great challenge in scan-based testing. Much previous research focused on shift power reduction, only a few papers took capture power into consideration. In capture mode, excessive IP-drop may occur due to the high switching activity thus lead to circuit malfunction and yield loss. In this paper, a new algorithm is proposed with using clock gating technique on a part of the scan cells to prevent the internal circuit from unnecessary transitions. These scan cells are divided into several exclusive scan groups. For each test vector, only a portion of the scan groups are activated to store the test response in single capture cycle. The proposed method can reduce the capture power dissipation without any influence on fault coverage or testing time, and with a little impact on circuit area. Experimental results for ISCAS’89 benchmark circuits show that the average capture power reduction in test sequence can be up to 40% and hardware overhead is approximately 5.49%.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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