| 摘要: | 近年來，離散小波轉換 (Discrete Wavelet Transform，簡稱DWT)，目前已成功地被應用在各種領域，包括數值分析、信號分析、影像編碼、紋理辨識與生物醫學等。由於離散小波轉換具有極佳能量集中的特質和與生俱來多重解析 (Multiresolution) 的特性，使它在影像及視訊壓縮編碼系統中受到極高的重視。
在多媒體IC硬體中，因為運算上的複雜，使得內部存取的記憶體 (On- chip memory) 變的很佔面積，而JPEG2000壓縮技術中，二維離散小波轉換就有此問題，但離散小波轉換在應用上需要很複雜的運算，而用硬體架構來實現離散小波轉換可以節省運算時間，因此VLSI架構的實現變得相當重要。
在本論文中，我們透過介紹JPEG2000中二維離散小波轉換 (2-D Discrete Wavelet Transform) 之演算法，提出VLSI架構設計與實現，在電路設計上，我們特別考慮到影像邊緣效應的處理，藉由適當的映射硬體電路之設計，可使影像反轉時更接近原始影像，硬體設計以低記憶空間及高工作頻率為目標，為達此目標我們提出了交叉讀取掃瞄演算法 (Interlace Read Scan Algorithm, IRSA)，以平行小波轉換器處理方式達成低記憶空間並減少其時脈週期，據此，我們設計了一個提昇式5/3無失真離散小波轉換器。它可以有更低計算的複雜度，且有規則的資料流，很適合做為VLSI的實現，可應用於JPEG 2000和MPEG- 4的及時影像/視訊處理。
為了驗證設計的架構，我們使用TSMC 0.35.um 1P4M CMOS製程實作晶片。此二維離散小波轉換所用的記憶體容量在計算N×N的二維影像上只需要N的儲存空間，這大約是JPEG2000標準中儲存空間的一半，且工作頻率可達到100MHz。
In the last few years, discrete wavelet transform (DWT) has been widely and successfully used in many fields, such as numerical analysis, signal analysis, image coding, pattern recognition, and biometric. Since DWT has excellent features of energy compaction and inherent Multiresolution, it has been applied extensively in the field of image and video compression.
Usually people 2-dimensional (2-D) DWT to accomplish their applications. However, 2-D DWT needs very intensive computation and massive memory. For real-time applications the 2-D DWT is usually hardwarized. For hardware implementation, to reduce the computation complexity and memory requirement becomes an very important issue.
This thesis tries to find some new algorithms and hardware architectures to improve the 2-D DWT. We present a low memory and high speed VLSI architecture for 2-D lifting-based lossless 5/3 filter discrete wavelet transform. The architecture is based on the proposed interlaced read scan algorithm (IRSA) and parallel scheme processing to achieve low memory size and high speed operation. The proposed lifting-based DWT architecture has the advantages of lower computational complexity. Meanwhile, our architecture can also provide embedded symmetric extension function, and regular data flow, and is suitable for VLSI implementation. It can be applied to real time image/video operating of JPEG 2000 and MPEG- 4 applications.
To verify the performance of our proposed architecture, we designed and simulated a 2-D DWT VLSI chip by TSMC 0.35um 1P4M CMOS technology. In our proposed VLSI architecture, to compute an N×N 2-D DWT using 5/3 filter requires only N storage cells and this memory bandwidth requirement is almost one-fourth of the JPEG 2000 proposal and it can operate at 100MHz clock frequency. The proposed VLSI architectures are designed in Verilog HDL, and syntesized by the Synopsys Design Compiler. Finally, the layout of the design is generated automatically by Avant! Apollo Layout Tools in a TSMC 0.35μm 1P4M CMOS technology. |
