Due to the fact that cache memory has high hit rate and low access time, the cache memory has been an important memory device to reduce the speed gap between the processor and main memory in computer systems, and further reduce the average access time of the entire system. In recent years, thanks to the continuous progresses in VLSI technologies, many computer systems are trending to the development of the integrated systems such as embedded systems, system on chip, or multiprocessor systems. However, low power consumption is an essential requirement for these systems. If the energy dissipation during cache access can be reduced, there exists a significant improvement in the overall power consumption of computer systems due to that processors access the cache memory so frequently. Therefore, how to design high-performance and low-power caches is an important issue for the modern computer architectures.
In the past, there were many researches devoted to the design of high-performance and low-power caches. In this dissertation, we focus on the often-used set-associative cache architectures, and propose several high-performance and low-power designs for serial and parallel cache types, respectively. For example, valid-bit pre-decision and MRU block list are used to eliminate the unnecessary access number of tag memory and data memory, and thus the improvement of the conventional sequential MRU cache in average access time and energy dissipation can be achieved. Based on the same idea, a new way-predicting cache using valid-bit pre-decision is proposed to progressively improve the energy dissipation and access time of the conventional way-predicting cache, especially for the cache with large associativity. Besides, we propose a set-associative cache that can provide the flexibility to configure its associativity according to different program behaviors; such that this configurable-way cache can save more energy while its performance is still maintained as same level as that of the conventional set-associative cache. Moreover, the proposed configurable-way cache can be used in the multiprocessor system to reduce the overall power consumption.