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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/35708

    Title: Designs of high-performance and low-power cache architectures
    Other Titles: 高效能及低功率快取記憶架構之設計
    Authors: 陳信全;Chen, Hsin-chuan
    Contributors: 淡江大學電機工程學系博士班
    江正雄;Chiang, Jen-shiun
    Keywords: 平均能量損耗;平均存取時間;循序式MRU快取記憶體;有效位元預先決定;組路預測快取記憶體;可調整組路快取記憶體;可規劃組路快取記憶體;average energy dissipation;average access time;sequence MRU cache;valid-bit pre-decision;way-predicting cache;adjustable-way cache;configurable-way cache.
    Date: 2005
    Issue Date: 2010-01-11 07:02:39 (UTC+8)
    Abstract: 在電腦系統中,由於快取記憶體有著高命中率及低存取時間的特性,因此快取記憶體一直都是用來解決CPU與主記憶體間存取速度落差,並進而減少系統的平均存取時間之重要記憶元件。近年來,拜賜超大型積體電路技術不斷地進步,許多電腦系統已朝向發展嵌入式系統、晶片系統,或是多重處理器系統,然而對這些系統而言,低功率損耗的需求更是迫切地重要。由於CPU存取快取記憶體十分頻繁,而若能降低快取記憶體於存取時之能量消耗,將對整體電腦系統功率損耗的改善有著明顯的助益。因此,在現在電腦結構中,如何設計高效能和低功率的快取記憶體便成為一個重要的議題。在過去有許多有關於高效能或低功率快取記憶體的發展研究,於本論文中,我們將以常用之集結合映射快取記憶體架構為主,分別針對循序式及平行式兩種快取記憶體型態,提出幾種高效能及低功率快取記憶體設計。其中包括:利用有效位元預先決定方法,並配合序列的MRU組路紀錄,可以減少不必要的標記及資料記憶體的存取次數,進而改善傳統循序式MRU快取記憶體的平均存取時間與能量消耗。相似的方法亦可應用至平行式的組路預測快取記憶體,並配合單一MRU組路的預測,便可避免啟動不必要之標記及資料記憶陣列數量。如此對於高關聯度的快取記憶體而言,將進一步有效地改進傳統組路預測快取記憶體的效能與能量。此外,我們也提出一種可依執行程式行為區域性的不同,而彈性調整其關聯度之快取記憶體。此一可規劃組路的快取記憶體不僅可節省能量消耗,亦能維持與傳統集結合快取記憶體相同的存取時間;進而可應用於多重處理器系統中,以降低系統整體功率。
    Due to the fact that cache memory has high hit rate and low access time, the cache memory has been an important memory device to reduce the speed gap between the processor and main memory in computer systems, and further reduce the average access time of the entire system. In recent years, thanks to the continuous progresses in VLSI technologies, many computer systems are trending to the development of the integrated systems such as embedded systems, system on chip, or multiprocessor systems. However, low power consumption is an essential requirement for these systems. If the energy dissipation during cache access can be reduced, there exists a significant improvement in the overall power consumption of computer systems due to that processors access the cache memory so frequently. Therefore, how to design high-performance and low-power caches is an important issue for the modern computer architectures.
    In the past, there were many researches devoted to the design of high-performance and low-power caches. In this dissertation, we focus on the often-used set-associative cache architectures, and propose several high-performance and low-power designs for serial and parallel cache types, respectively. For example, valid-bit pre-decision and MRU block list are used to eliminate the unnecessary access number of tag memory and data memory, and thus the improvement of the conventional sequential MRU cache in average access time and energy dissipation can be achieved. Based on the same idea, a new way-predicting cache using valid-bit pre-decision is proposed to progressively improve the energy dissipation and access time of the conventional way-predicting cache, especially for the cache with large associativity. Besides, we propose a set-associative cache that can provide the flexibility to configure its associativity according to different program behaviors; such that this configurable-way cache can save more energy while its performance is still maintained as same level as that of the conventional set-associative cache. Moreover, the proposed configurable-way cache can be used in the multiprocessor system to reduce the overall power consumption.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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