佈局對高壓靜電防護能力影響與驗證

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Thesis > Item 987654321/35699

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Title:	佈局對高壓靜電防護能力影響與驗證
Other Titles:	To verify the effect upon the device's ESD when modifying the HV MOS layout
Authors:	張純;Chang, Chun
Contributors:	淡江大學電機工程學系碩士在職專班李揚漢;Lee, Yang-han
Keywords:	靜電放電;人體放電模式;機器放電模式;傳輸線觸波產生器;ESD;HBM;MM;TLP
Date:	2009
Issue Date:	2010-01-11 07:02:03 (UTC+8)
Abstract:	高壓製程廣泛地應用在驅動電路(driver circuits)、視訊通訊 (telecommunication)、電源開關(power switch)及汽車面板(motor control system)等等的應用. 在驅動電路技術中，高壓的金氧半場效電晶體通常拿來當做靜電放電的保護元件，除此之外同時還可以當做輸出級的驅動元件(output driver )，由於高壓的操作電壓較高，使得高壓的金氧半場效電晶體之靜電放電能力比低壓的金氧半場效電晶體之靜電放電來的低，因此靜電放電可靠度的問題在高壓金氧半場效電晶體製程中製作的積體電路產品也變的非常重要。除此之外高壓元件的耐壓能力也是另一考量，增加元件崩潰電壓的方式可改由元件製程上著手，可藉由改變元件的飄移摻雜(drift)的離子植入濃度、劑量，或元件接面的曲度(curvature)、通道長度、製程材料等條件，以便增加元件的崩潰電壓；但以一般IC設計公司而言改變製程條件是不可行的，因此本論文只能利用佈局(layout)參數變化，使得高壓之金氧半場效電晶體有較高的崩潰電壓以及較好的靜電放電防護能力，而且不需增加額外光罩或上述各種改變製程方式。本論文中，會說明高壓金氧半場效電晶體元件的詳細失效機制(Failure Mechanism)，瞭解其失效機制後針對失效點做改善，目前已有方法有效地使寄生於N型橫向擴散高壓金氧半場效電晶體的載子延緩進入導通狀態，其方法在汲極端下方增加N型坡度摻雜(N-grade)距離，並可有效地增加崩潰電壓，但汲極端接觸點到閘極距離不變，亦不需增加額外光罩，且和晶圓廠所提供的設計規範做比較，在N+內縮之後對靜電放電(ESD)能力及崩潰電壓有何影響及其趨勢。本實驗使用聯華電子0.6微米之30伏特的高壓金氧半場效導體製程。 HV processes are widely applied in driver circuits, power switches, telecommunications, and motor control systems, etc . Among driver circuit technology, HV MOS are usually used to be the ESD protection device and the driver of output stage. Because of the high operation voltage, the ESD level of HV MOS is lower than LV MOS. Therefore, ESD reliability of IC products is very important when using HV MOS process. In addition, the high voltage resistance capability of HV device is another important issue. By modifying the process, there are many ways to improve the breakdown voltage of the devices, such as modification of ion implement concentration, dosage, device interface curvature, channel length, process material, etc. However, to change the conditions of the process is impractical for general IC design houses! In this paper, we can only change the layout parameters to improve the breakdown voltage and ESD level of HV MOS and it doesn’t need to add extra mask layer or do any process changing. In the work we’ll describe the detail failure mechanism of HV MOS and do some improvement after understanding the failure mechanism. In the present day, there is an effective way to slow down the carrier that is parasitical in NMOS into conductive mode. The ways efficiently improve breakdown voltage by increasing the N-grade distance under the drain terminal and it doesn’t need to change the DCG distance or add extra mask layer. After comparing with the design rule that is provided by the foundry, we can realize the effects and trend after shrinking the N-plus area. This experience uses UMC 0.6um 30V HV MOS process.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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