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    Title: 使用動態偏壓電路之低功率三角積分調變器於音頻之應用
    Other Titles: Low power sigma-delta modulator with dynamic biasing for audio applicaton
    Authors: 李宜昇;Lee, Yi-sheng
    Contributors: 淡江大學電機工程學系碩士班
    余繁;Ye, Fun
    Keywords: 動態偏壓;三角積分調變器;音頻;切換電容電路;Dynamic Biasing;Sigma-Delta modulator (SDM);Audio;Analog-to-digital (A/D) conversion;Switched-Capacitor Circuit
    Date: 2007
    Issue Date: 2010-01-11 07:00:44 (UTC+8)
    Abstract: 在日常生活中,聲音傳遞對於人與人之間的溝通是相當重要的。有鑑於此,我們所設計的類比/數位轉換器(A/D Converter),便以音頻(Audio)為應用範圍。我們利用超取樣(Over Sampling)和雜訊移頻(Noise Shaping)的技術,完成了這個三角積分調變器(Sigma-Delta Modulator, SDM),來進行類比與數位訊號間的處理及轉換。而這一類的類比/數位轉換器,最初即是運用在音頻方面,可以充份發揮其高解析度及對於類比電路的較不敏感。因此,所需電路較不複雜,在功率的消耗上對於其它類別的類比/數位轉換器而言,也相對較低。
    目前音頻方面的類比/數位轉換器,主要運用的範圍,不外乎是手機、MP3播放器等等。與聲音相關的可攜式電子系統。因此,除了轉換的解析度(Resolution)必須達到音頻的標準外,在消耗的功率方面,也是一個重要的考量。一般常見降低功率的方法,就是使用低電壓的架構,利用低電壓的先天優勢,來達成減低功率的目的。然而,隨著製程的不斷進步,雖然電壓可以持續的降低,但相對而言,一些物理特性的考量勢必更為嚴苛,在電路的實現方面,也將更加的複雜。往往需要增加一些額外的電路,來達到所需的目標,自然在功率方面也會有所消耗。本文中,我們所採用的是動態偏壓(Dynamic Biasing)的方法。藉由此電路,使電流在不同的區間中,有其適當的電流值。相對於未使用動態偏壓時,消耗的功率自然會有所降低。
    我們設計的三角積分調變器,是以切換電容電路(Switched-Capacitor Circuit)為主,在了解及分析整個電路後,我們發現,在運算放大器動作的過程中,可以區分為兩個時序,一為取樣(Sampling)、二為保持(Holding)。其中,取樣的部份還可分為兩個部分,廻轉(Slewing)及穩定(Settling),廻轉與廻轉率(Slew Rate)有關,而穩定則與運算放大器的頻寬(GBWOP)有關。一般在設計電路時,是以所需的最大電流為基準。然而,根據相關的公式推導及分析,我們可以發現,在廻轉與穩定狀態時,考量廻轉率、頻寬及準確度(Accuracy)等等…不同的條件下。經由Matlab的分析模擬後,可以得到最小功率之切換時間,再根據切換時間的不同,廻轉及穩定的電流亦有所不同。便可利用切換電路來達成,在某一切換時間下,切換電流的大小。在比較原本使用單一最大電流時,在功率消耗方面,自然會減少。

    另一方面,在相位部份,切換電容電路在不同的相位時,回授係數(Feedback Factor)的不同,所掛載的電容值亦不相同,所需要的電流值自然會有改變。切換電路亦可運用在這方面,在不同的相位時,求出相對應的電流值,在消耗的功率方面,也會有所降低。
    在整體的電路上,也因為切換電路的關係,配合分析而得的電流最佳值。在比較一般的設計方法,以單一最大電流來決定整體的電流值,對於消耗功率的減少上,有一定的助益。此外,因為動態偏壓電路,僅需增加一組簡單的切換偏壓電路,對於整個系統而言,並不會在功率上有太大的消耗。在評估過後,整體的功率消耗,約可節省整體系統百分之二十的功率。
    最後,我們採用四階串接(Cascade)(2-2 MASH)的三角積分調變器架構,以TSMC 0.35um 2p4m 標準製程來實現整體電路,工作電壓為3V,寬頻為25KHz,取樣頻率為3.2MHz,超取樣比為64。模擬結果顯示在取樣頻率為3.2MHz下其動態輸入範圍為95dB,而最大的訊號雜訊失真比為93dB,總功率消耗5mW。
    The analog-to-digital (A/D) converters play an important role in the application of the audio systems. We use the over-sampling and noise shaping techniques to complete the Sigma-Delta (ΣΔ) Modulator, which is used to process and convert the analog signal to digital one. First, as the Sigma-Delta (ΣΔ) Modulator has the properties of high resolution and low sensitivity, it is used mostly in speech and audio application. Thus, the requirement of the Sigma-Delta Modulator is not that critical. And consequently, the power consumption of such system is relatively lower than other A/D converters.
    At present, the A/D converters for audio application are used mostly in cell-phone, MP3 player etc. These portable electronics systems are relative with audio. Hence, besides that the resolution has to achieve the audio application, i.e. 16bits, the power consumption is a very important consideration. In general, the method to decrease power is using the low voltage architecture and therefore achieving the low power. However, even though the supply voltage can be decreased with the growth of the process technology, the physical characteristics will be complicated, and the circuits will be more difficult to design. In our thesis, we will introduce a dynamic biasing method. With such method, we can obtain the optimum current in different regions. In contrast to fixed biasing method, the power dissipation will be decreased.
    Generally, the Sigma-Delta (ΣΔ) Modulator is implemented with the Switched-Capacitor Circuit. After analyzing the whole circuit, the operation of the SC circuit can be separated into two modes, i.e., sampling mode and integrating mode. The integrating mode also can be separated into two parts, and one of it is slewing and the other is settling. Slewing is related with slew rate of the opamp, while settling is related with opmap’s gain bandwidth. Generally, we choose a larger current for the criterion. However, according to the derived formulas, we can find out the relationship between the slewing mode and the settling mode.
    Through the simulation with MATLAB, we can obtain the minimum power for a switching timing. According to the switching timing, we can get the different currents in slewing and settling modes. Then, we use the dynamic biasing circuit to switch the current. Compared with the fixed biasing circuit, the power consumption with dynamic biasing circuit can be certainly reduced.
    In addition to different mode, there are different feedback factors in switched-capacitor circuit. Thus, the loading capacitor and related current will be changed. We can also use the dynamic biasing circuit to switch the current during the sampling mode. The power dissipation will be therefore decreased.
    By only adding a simple dynamic biasing circuit, the power consumption will then be reduced. After evaluating the power consumption, the power savings of opamps are about 30%.
    In this thesis, we design a fourth-order cascade (2-2 MASH) Sigma-Delta Modulator. The dynamic range and SNDR can be 95dB and 93dB, respectively. The power dissipation is 5mW. It was implemented by the TSMC 0.35um 2p4m process with 3-V supply.
    Appears in Collections:[電機工程學系暨研究所] 學位論文

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