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    題名: Low-power/high-speed scalable and subchannelizable FFT architecture for SOFDMA application
    其他題名: 用於WiMAX中SOFDMA應用之低功率高速度可多點數化暨可子通道化快速傅利葉轉換器架構
    作者: 李育師;Lee, Yu-shih
    貢獻者: 淡江大學電機工程學系碩士在職專班
    江正雄;Chiang, Jen-shiun
    關鍵詞: 可規劃接取正交分頻多工;快速傅利葉轉換;SOFDMA;FFT
    日期: 2006
    上傳時間: 2010-01-11 06:59:47 (UTC+8)
    摘要:  隨著無線可攜式產品的需求亦加殷切,低工率晶片設計成為一項值得研究的課題,另外,WiMAX的堀起更引發一股SOFDMA的研究熱潮。本論文揭露一種可用於SOFDMA領域的低功率FFT架構。
      SOFDMA是Scalable Orthogonal Frequency Division Multiple Access的縮寫。可多點數化(Scalable)使得WiMAX系統能配合外在環境的變化適時地調整FFT的點數以達到最有效率而又符合最低QoS要求之通訊傳輸。多用戶接取(Multiple Access)使得WiMAX能夠在給定頻譜範圍內單點對多點地進行互通傳輸,本架構即是利用多用戶接取特性設計可子通道化(Subchannelization)之FFT處理器。
      由於晶片製程的進步,晶粒屬性有些已從核心侷限型(Core limited)導向焊盤侷限型(Pad limited),面積已非電路設計的首要考量,因此,本論文提出快閃式架構,致使處理器設計同時符合低功率與高速度兩項要求。另外,為了降低功率控制機制的複雜度,本架構提出一種記錄式方法(Registry Method)。
      妥善的非同步設計能夠同時提供低功率與高速度兩項好處,基於此,本架構的FFT核心部分採用的是非同步設計,伹電子設計自動化工具(EDA)廠商近十數年來的研究重點皆著重在同步設計,因此,本發明在非同步核心之外係用同步電路予以包裹,目的在於晶片系統(SOC)設計時的穩健性與易整合性。
      本論文的重心在於架構設計與功耗估算,主要是用MATLAB程式寫成,分別針對IEEE 802.16e WiMAX和IEEE 802.16-2004 WiMAX所需的128/512/1024及256/2048點FFT評估採用本架構時,興一般FFT處理器相比較所能節省下來的功率(高達80%至98%)。為了便於晶片實現所需,更以Agilent® ADS製作一可即調即跑式(tunable)模擬環境,便於設計者估算可能耗散的功率。
    An inventive FFT architecture, which is both scalable and subchannelizable, is provided with low-power and high-speed characteristics for SOFDMA application in IEEE 802.16 WiMAX communication protocol and other fields that have features in SOFDMA applications.
    OFDMA (Orthogonal Frequency Division Multiple Access) is a multiple access scheme for OFDM systems. OFDMA works by assigning a subset of subcarriers to individual users. SOFDMA is a scalable version of OFDMA, the point number of FFT processors are scalable in sessions. Scalability is required to adapt FFT point number to changing channels, and subchannelizability is required for MA (Multiple Access).
    As the chip manufacturing process becomes more and more advanced, the die size is less critical than before. For the increasing demands in portable devices, low-power feature becomes the critical issue in chip design. Therefore, unused arithmetic operations are prohibited in the present inventive design to achieve low-power requirement because only a small subset of FFT outputs are of interests for a specific SS (Subscriber Station) in one session of a IEEE 802.16e or IEEE 802.16-2004 WiMAX systems. It is the spirits of the present subchannelization design.
    IEEE 802.16e and IEEE 802.16-2004 WiMAX systems requires scalability in FFT processing for 128/512/1024 and 256/2048 points. The present scalability design uses multiplexing concept to build only one 1024-point and only one 2048-point FFT processors in an IEEE 802.16e and an IEEE 802.16-2004 WiMAX systems, respectively.
    Registry method and Sync-Async architecture are also disclosed for the purposes of structure simplification and low-power/high-speed designs. The performance on areas and power efficiency are analyzed based on MATLAB codes. A closed system platform is used to tune design parameters for chip implementation by using Agilent® ADS (Advanced Design System) tool.
    顯示於類別:[電機工程學系暨研究所] 學位論文

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