在本篇論文中，我們使用了平均分配(balance)和限制最長子字串的方法(constraint longest common subsequence)減少在傳播掃描架構中樣本集與時間成本的大小。我們嘗試在每個待測電路掃描鍊中，平均分配一對相同位址且有最多相似內容的正反器。
為了證明所提出的方法是有效的，我們使用ISCAS''85benchmark組合電路和ISCAS''89 benchmark序向電路做模擬，實驗結果顯示我們的方法能夠有效減少樣本集與時間成本的大小。我們只需297組樣本集即可發現ISCAS''85 benchmark組合電路所有的錯。在序向電路方面，只需1322組樣本集即可發現ISCAS''89 benchmark電路所有的錯。 The scan-based techniques require scan the test stimuli to scan chain and analyze the output responses. The test application time for the scan-based circuits is proportional to the product of the number of test patterns and the length of the scan chain. In a modern VLSI circuit, the increased design complexity results in longer and longer scan chains. Hence, in a typical scan structure, scan operations usually require a long test application time. The increased test application time significantly increases the cost of testing a scan-based design. Hence how to reduce test application time has become an important issue when a scan base design is used.
The single scan chains technique have the long test application time. Multiple scan chains techniques have been developed to alleviate the long test application time problem. By dividing a single serial scan chain into a number of shorter scan chains test patterns and test results can then be shift in/out of all chains in parallel to reduce the test application time. This method, however, will require a much higher number of extra I/O pins.
A approach called the broadcast scan can share the test stimulus for a single input to support multiple scan chains. By appropriately connecting the inputs of all circuits under test during ATPG process such that the generated test patterns can be broadcast to all scan chains.
In this paper we shall describe a broadcast scan architecture that can reduce the test pattern and test application time. Based on the balance and constraint longest common subsequence method. There, our method tries to balance assign pairwise similar flip-flops to the same position in each CUT scan chain.
To verify the effectiveness of the proposed method, experiments on the ISCAS’85 combinational benchmark circuits and the ISCAS’89 sequential benchmark circuits. The result show can reduce the test pattern and test application time. It is found that we only need 297 test patterns to detect all detectable faults in all five ISCAS’85 combinational circuits. For the sequential circuits, we show that with our method, 1322 test patterns are enough for the five ISCAS’89 scan-based sequential circuits.
