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    Title: The hardware implementation of genetic algorithm accelerator and its optimization applications in communication and high speed printed circuit board
    Other Titles: 基因演算加速器硬體實現及其在通訊與高速電路板之優化應用
    Authors: 周允仕;Chou, Yun-hsih
    Contributors: 淡江大學電機工程學系博士班
    李揚漢;Lee, Yang-han
    Keywords: 基因演算法;封包排程;高密度分波多工;次通道化排程機制;高速電路板;電源系統阻抗;電源雜訊;介電係數;耗損係數;四分之一波長開路短枝共振腔;Genetic Algorithm;Packet Scheduling;DWDM;IEEE 802.16;Subchannelization Scheduling;PCB;Power Bus Impedance;Ground Bounce;FR4;Dielectric constant;Attenuation Constant;Quarter-wavelength Open Stub Resonator
    Date: 2009
    Issue Date: 2010-01-11 06:59:41 (UTC+8)
    Abstract: 本論文主要利用基因演算法分別針對高密度分波多工(DWDM)之光纖通訊網路之封包排程、IEEE802.16正交分頻多路存取(OFDMA)次通道化排程機制及高速電路板(HSPCB)抑制電源雜訊去耦合電容數量選取等三種不同的系統提出解決的方法。
    第一部分,我們是以基因演算法的架構提出一種改良的、可實現於可規劃的邏輯陣列元件(FPGA)的封包排程硬體架構,利用這樣的架構可以提升高密度分波多工技術(DWDM)在封包排程當中找到最佳化排程的速度,以實際提升使用之光纖通訊網路之效率。
    第二部份,我們提出一個使用基因演算法在IEEE802.16正交分頻多路存取(OFDMA)次通道化排程機制上的解決方案。此解決方法能快速地收斂且獲取多使用者傳輸的機制下,下傳鏈路次訊框的最短傳輸時間排列方式。並且設計及實現於可規劃的邏輯陣列元件(FPGA)的硬體架構,利用這樣的硬體架構來實現多使用者之傳輸狀況下,能獲得下傳鏈路次訊框的最短傳輸時間之排列方式,並提升其傳輸的效能與降低所花費的成本。
    在高速印刷電路板設計上,電源雜訊干擾問題的解決可以採用加上去耦合電容來解決及採用電源層切割或隔離電源板層技術。所以第三部份我們使用基因演算法來預估最少需使用的去耦合電容數目,不僅可以節省成本及佈局面積,亦可降低經驗決定的因素。在此部分,我們首先探討四分之一波長開路短枝共振腔之量測技術,並獲得印刷電路板介質材料的介電係數及衰減係數。緊接著使用網路分析儀(VNA)及模擬軟體完成高速電路板的金屬電阻耗損係數、介電材質耗損係數及有效介電係數的萃取。我們利用獲取之參數建構完成電源板層的等效電路模型,可提供未來設計電源系統阻抗的參考,並進一步使用基因演算法及HSPICE模式化的計算方式完成抑制電源雜訊去耦合電容數量最佳化的選取。最後,我們亦探討電源隔離島及切割等常用之隔離技術來探討降低干擾的問題來源。
    In this dissertation we mainly utilize the principle of Genetic Algorithm to find the solutions for the problems encountered in the following three systems: the Packet Scheduling in optical communication network systems with Dense Wavelength Division Multiplexing (DWDM); the sub-channelization scheduling mechanism in the IEEE 802.16 Orthogonal Division Multiplexing Access (OFDMA) system and the determination of the number of decoupling capacitors needed to mitigate the power source noise in the high speed printed circuit board (HSPCB).
    In the first part we base on the principle of Genetic Algorithm to propose an improved and realizable field programmable gate-array (FPGA) hardware architecture in the implementation of the Packet Scheduling problem. By simulating this architecture we can improve and find the optimal scheduling speed for the packet scheduling problem in the Dense Wavelength Division Multiplexing (DWDM) system to effectively improve the transmission efficiency when data is transmitted through of the optical communication network.
    In the second part we propose to utilize the Genetic Algorithm to find the solution to the problem of sub-channelization scheduling in the IEEE802.16 Orthogonal Frequency Division Multiplexing Access (OFDMA) system. This solving method can be in the shortest time period to determine the scheduling of the transmission of downlink sub-frames under the criterion of converging fast and to acquiring the transmission of more users. We then describe the design procedure to propose an improved and realizable FPGA hardware architecture and then to utilize this architecture under the criterion of transmitting as many as users as possible to find in the shortest time period the scheduling of the transmission of downlink sub-frames and to improve the transmission efficiency and to reduce the system cost.
    In the high speed printed circuit board design it can implement two methods to solve the power-bus noise interference problem. One method is by adding decoupling capacitors in the circuit board and the other method is to adopt the technique of power bus isolation or power plane segmentation. In the third part of this dissertation we try to employ the Genetic Algorithm to estimate the minimum number of decoupling capacitors required in multilayer printed circuit board; it results in not only to reduce the system cost and to minimize the required circuit board layout area, but also to decrease the dependence on empirical experience in the selection of capacitors. In this part we first investigate the measurement technique of using a quarter- wavelength open stub resonator and to obtain the dielectric constant and the loss factor of the dielectric material. In the sequel we will use the vector network analyzer (VNA) and the simulation software to complete the measurement and calculation of the transmission line’s conductor loss, dielectric constant, the dielectric loss and the effective dielectric constant of the high speed circuit board. We then from the extracted parameters to build an equivalent circuit model of the power-bus layer and this equivalent circuit model can be employed in the future as a reference in the impedance design of the power bus system. We will further to exploit the Genetic Algorithm and the calculation method of the modularized HSPICE tool to optimize the number of decoupling capacitors required in the mitigation of the power source noise. We also investigate the commonly employed techniques such as the power isolation island and the segmentation in the reduction of the interference sources.
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Thesis

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