A novel reseeding mechanism for pseudo-random testing of VLSI circuits

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Thesis > Item 987654321/35673

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Title:	A novel reseeding mechanism for pseudo-random testing of VLSI circuits
Other Titles:	使用新型種子值重設技巧之超大型積體電路假性隨機測試法
Authors:	何應甫;Ho, Ying-fu
Contributors:	淡江大學電機工程學系碩士班饒建奇;Rau, Jiann-chyi
Keywords:	內建自我測試;假性隨機測試向量;重設種子值;測試長度;單一定值錯誤;錯誤函蓋率;BIST;Pseudo-Random pattern;reseed;test length;single stuck-at fault;fault coverage
Date:	2005
Issue Date:	2010-01-11 06:59:37 (UTC+8)
Abstract:	近代的設計與封裝技術快速發展，已使得單晶片系(System-On-a-Chip，SoC)成為一個趨勢，由於它是將整個系統所能執行的功能都由一矽晶片來實現，以至於要從外部來測試系統有沒有發生錯誤和缺陷變的非常困難了。所以大部份的設計者在設計晶片的過程中就會將測試的電路也一並加入，也就是所謂的可測試設計(Design for Testability，DFT)。內建自我測試(Built-In Self-Test，BIST)是屬於可測試設計(DFT)的其中一種方法。在BIST的架構裡包含了測試結果壓縮器(response components)，信號分析器(signature analyzer)，測試向量產生器(test pattern generator，TPG), 在此我們所使用的是線性回溯移位暫存器(Linear Feedback Shift Register，LFSR)。但是，由線性回溯移位暫存器所產生的測試向量，可能無法得到較高的錯誤涵蓋率(Fault Coverage), 而且，一些無效的測試向量(useless pattern)也會使得測試時間(test time)變長，因為我們使用了重新設定種子值(Reseeding)的技巧，修正測試向量的某些Bits(modify pseudo-random bit)，和一個額外加入的計算器，來將錯誤涵蓋率提升到趨近於100%，並同時將測試長度(test length)縮短，亦即測試時間(test time)降低。重新設定種子值(Reseeding)的方法主要是拿來跳過沒有用的測試向量(useless pattern)，以縮短測試的時間。修正測試向量的某些Bits(modify pseudo-random bits)的方法是當無效的測試向量(指無法偵測到錯誤的測試向量)要傳遞到掃描鏈的時候，經由修改數個bits後，變成有用的測試向量(useful pattern),以縮短測試時間和增加錯誤涵蓋率。額外的計數器則是用來計數在何時有用的測試向量值會正好傳遞到掃描鏈(Scan Chain)上，而去捉取他的輸出值以降低測試時間。結合以上三種方法可以將錯誤涵蓋率有效的提升和縮短測試所需的時間。 During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault (useless patterns). In order to reduce the test time, we can remove useless patterns or change from them to useful patterns (fault dropping). In this paper, we reseed, modify the pseudo-random and use an additional bit counter to improve test length and achieve high fault coverage. The fact that a random test set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we pick out number of different less bit, leading to very short test length. And We can use an additional bit counter to control the scan enable signal for capturing (when the useful pattern is loaded into the scan chains). The technique we present is applicable for single-stuck-at faults. The seeds we use are deterministic so 100% faults coverage can be achieved. Modern design and package technologies make external testing increasingly difficult and the built-in self-test (BIST) has emerged as a promising solution to the VLSI testing problem. BIST is a design for testability methodology aimed at detecting faulty components in a system by incorporating test logic on-chip. The main components of a BIST scheme are the test pattern generator (TPG), the response compactor, and the signature analyzer. The test generator applies a sequence of patterns to the circuit under test (CUT), the responses are compacted into a signature by the response compactor, and the signature is compared to a fault-free reference value. In this paper, we used an additional bit counter to control the scan enable signal. When the counter achieve to zero, it means that the useful pattern is loaded to the scan chain, so we can disable the scan enable signal for capturing. We pay the price in hardware overhead in order to decrease test length.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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