The design of low-power high-speed low-noise PFD_CP_SC_PLL

機構典藏 > College of Engineering > Graduate Institute & Department of Electrical Engineering > Thesis > Item 987654321/35671

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Title:	The design of low-power high-speed low-noise PFD_CP_SC_PLL
Other Titles:	低耗電高速低雜訊PFDCPSC鎖相迴路之設計
Authors:	鄭慎元;Cheng, Sheng-yuan
Contributors:	淡江大學電機工程學系碩士在職專班余繁;Ye, Fun
Keywords:	PFD_CP_SC式相角鎖相迴路;接收器;相位偵測器;迴路過濾器;電流饑渴式電壓控制振盪器;D式正反器;除法器.;PFD_CP_SC_PLL;Receiver;Phase-Detector;Loop-Filter;Source-Couple VCO;D-flip flop;Divider
Date:	2007
Issue Date:	2010-01-11 06:59:30 (UTC+8)
Abstract:	低耗電高速低雜訊無線PLL 積體電路為近年來業界所發展的主要產品之一. 它的市場很大所以引起了各家廠商的投入., 所以它的規格要求可以說是要求很高. 不但要低耗電, 以維持長的電池使用時間及待機時間比其他廠商來得長; 也要求高速的下載速度及上載速度. 以提供更佳的文字或圖形傳送, 甚至是音樂資料或影片檔案的下載. 本文PFDCPSCPLL 可達4 Giga Hz, 1.47E-02 Watts, and 6.9E-19 SQ V/HZ使用了Phase Frequency Detector, Chare Pump Filter, Source Couple VCO 和 N Divider, 提供了完整低耗電高速低雜訊PFDCPSCPLL 設計的要點及大綱, 讓通訊積體電路或系統的設計者有一參考文獻. The Low-Power High-Speed Low-Noise PLL is a significant circuit for portable consumer devices. There are many sorts of PLLs due to its huge market demand. Its main applications are portable phones and GPS devices. It requires low-power for allowing the battery has long-used time. Also it demands fast-download speed for text transmission or graphic transmission. Furthermore, it needs low-noise quality to assure excellent sound received quality. PFD_CP_SC_PLL can reach 4 Giga Hz, 1.47E-02 Watts, and 6.9E-19 SQ V/HZ composed by a Phase Frequency Detector, a Chare Pump Filter, a Source Couple VCO and a 64 Divider. This thesis offers a complete low-power, high-speed, and low-noise PFDCPSC PLL design concept and detailed circuits, allowing communication designers to have a great reference.
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Thesis

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