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請使用永久網址來引用或連結此文件:
https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/35653
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| 題名: | 快閃記憶體控制晶片的動態正規驗證方法 |
| 其他題名: | A dynamic formal verification methodology for flash memory controller |
| 作者: | 王將;Wang, Chiang |
| 貢獻者: | 淡江大學電機工程學系碩士班
簡丞志;Chien, Cheng-chih |
| 日期: | 2005 |
| 上傳時間: | 2010-01-11 06:57:30 (UTC+8) |
| 摘要: | 本篇論文以Verilog語言設計快閃記憶體控制器(Flash Memory Controller)，再以硬體化的testbench載入FPGA中進行實體驗證。
在各種應用層面下，不同的主機及介面(interface)結構因應而生，故快閃記憶體的控制器必需針對所在系統負責對外部主機(Host)溝通及內部資料的讀、寫、抹除等動作，故所設計的快閃記憶體控制器以多重的狀態機來自動執行主機端所下的指令，在資料的讀寫方面，針對快閃記憶體PAGE的大小，來設計控制器及選用的Buffer(SRAM)，指令的下達方面，以多重狀態機(multi-state machine)來處裡與快閃記憶體之間的回應。
控制器以Verilog語言描述完成後，依據欲測試項目寫testbench先作function simulation達到功能上的驗證，將原先的testbench硬體化，以便於在FPGA板上驗證，待一切設計完成後，緊接的步驟是電路合成，合成器將RTL Verilog程式讀入，依照我們選定的目標零件(Cyclone EP1C20F324C7)自動產生gate level netlists，並以此組檔案作Pre-Simulation，模擬測試通過後，再載入FPGA中進行實體驗證。
驗證結果顯示資料確實能從快閃記憶體中正常讀寫至特定位置，前面所提及的快閃計憶體控制器設計正確。
The thesis is established by Verilog language which designs flash memory controller, then hardware.testbench which loads in FPGA in order to process physical examination.
Different hosts and interfaces have been designed and developed in coordinate with broadly various kinds of applied environments,in one hand, flash memory controller shall specifically focus on the function that positioned.system is responsible for communication to external host as well as the procedures; reading, writing and deleting included; to internal data, in the other hand, flash memory controller designed by multi-state machine automatically executes instruction from the host. To mainly concentrate on the size of page of flash memory in conjunction with data reading and writing, proper controller is designed and selected.Buffer (SRAM) is applied, as the order of instruction, multi.state machine processes the reaction from flash memory.
Controller is finished by description of Verilog language afterwards, testbench is being written doing function simulation by examined items in order to achieve fuctional examination, then original testbench is being processing into hardware to be easily examined on FPGA board, after procedures listed above are done, the following step is synthesis, synthetic advice will read RTL Verilog program according to our selected target part(Cyclone EP1C20F324C7), it will automatically cause gate level netlists, pre.simulation is processing by the file which was produced by synthetic step above, after passing the simulation test, FPGA will be loaded in this file to process physical examination.
The result indicates that date indeed can be read and written on specific location from flash memory, therefore the design of flash memory controller mentioned is precise. |
| 顯示於類別: | [電機工程學系暨研究所] 學位論文
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