因為至今的高速運算以及多媒體應用盛行，在微處理器中的基本運算單元之設計就顯得相當重要。雖然除法器並不是最常被運用到的運算單元，但是它在算數運算單元中卻是扮演著相當重要的角色。位元遞迴的除法演算是一個簡易且常被運用的方法，為了加快運算的速度，我們可以增加基底數目來減少疊代運算的次數，若是採用基底β來運算，其中β=2m，則每次疊代運算可得到m位元的商數，所需要的疊代次數為n/m。我們提出了一個基底為八且相容於IEEE 754-1985的浮點運算除法器，整個除法器的運算是根據New Svoboda-Tung（NST）演算法以及基底為八的多餘數字系統。 除法器使用了無進位延遲的加法單元來完成簡單的遞迴運算，在運算元部份，是透過倍率單元來完成。我們整理了一個有系統的方法來完成倍率單元的設計，也提出了除法架構的硬體設計，在運算時間的複雜度方面是一個常數，不會因為位元長度而改變。在我們所設計的除法器中，因為運用了無進位延遲加法器，所以可以快速的處理任何位元的除法。在模擬結果中可知道，硬體電路的複雜度以及運算速度上的效能都比傳統SRT除法器來的好。 Due to the progress of high speed computation and multimedia application, the hardware implementation of all basic arithmetic operations becomes important in the design of microprocessor. Although division is not the most frequent arithmetic operation, Implementation of division is always one key point in arithmetic units. A simple and widely implemented class of division algorithm is digit recurrence. To speedup the division process, one may reduce the number of iteration steps by increasing the radix β of the process. Selecting β=2m allows the generation of m quotient bits at each step and the number of steps can be reduced to n/m. We propose a radix-8 floating point division that complies with the IEEE 754-1985. This method is based on New Svoboda-Tung（NST） algorithm and the radix-8 redundant number system. The divider involves a simple recurrence with carry-free addition and employs prescaling of the operands. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. By taking the advantage of the carry-free addition, we can perform any bit length divider in a fast easy manner. The simulation results show that the hardware complexity and performance of this divider is competitive with conventional SRT dividers.
