Test time reduction for scan-designed circuits by sliding compatibility

淡江大學機構典藏 > 商管學院 > 資訊管理學系暨研究所 > 期刊論文 > Item 987654321/21136

請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/21136

題名:	Test time reduction for scan-designed circuits by sliding compatibility
作者:	張昭憲;Chang, Jau-shien;Lin, Chen-shang
貢獻者:	淡江大學資訊管理學系
關鍵詞:	maximum overlapping condition;parity scan;postgeneration method;scan-designed circuits;sliding compatibility;test clocks;test time reduction
日期:	1995-01-01
上傳時間:	2009-11-30 13:15:08 (UTC+8)
出版者:	Institution of Engineering and Technology (IET)
摘要:	A postgeneration method for test time reduction of scan-designed circuits is developed. The maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity scan, the test clocks required by the authors' method are only 41% of those elsewhere.
關聯:	IEE proceedings. Computers and Digital Techniques 142(1), pp.41-48
DOI:	10.1049/ip-cdt:19951520
顯示於類別:	[資訊管理學系暨研究所] 期刊論文

文件中的檔案:

檔案	大小	格式	瀏覽次數
	0Kb	Unknown	303	檢視/開啟
index.html	0Kb	HTML	110	檢視/開啟
Test time reduction for scan-designed circuits by sliding compatibility.pdf	658Kb	Adobe PDF	2	檢視/開啟

在機構典藏中所有的資料項目都受到原著作權保護.

TAIR相關文章