Test time reduction for scan-designed circuits by sliding compatibility

淡江大學機構典藏 > 商管學院 > 資訊管理學系暨研究所 > 期刊論文 > Item 987654321/21136

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题名:	Test time reduction for scan-designed circuits by sliding compatibility
作者:	張昭憲;Chang, Jau-shien;Lin, Chen-shang
贡献者:	淡江大學資訊管理學系
关键词:	maximum overlapping condition;parity scan;postgeneration method;scan-designed circuits;sliding compatibility;test clocks;test time reduction
日期:	1995-01-01
上传时间:	2009-11-30 13:15:08 (UTC+8)
出版者:	Institution of Engineering and Technology (IET)
摘要:	A postgeneration method for test time reduction of scan-designed circuits is developed. The maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity scan, the test clocks required by the authors' method are only 41% of those elsewhere.
關聯:	IEE proceedings. Computers and Digital Techniques 142(1), pp.41-48
DOI:	10.1049/ip-cdt:19951520
显示于类别:	[資訊管理學系暨研究所] 期刊論文

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