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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/21136


    Title: Test time reduction for scan-designed circuits by sliding compatibility
    Authors: 張昭憲;Chang, Jau-shien;Lin, Chen-shang
    Contributors: 淡江大學資訊管理學系
    Keywords: maximum overlapping condition;parity scan;postgeneration method;scan-designed circuits;sliding compatibility;test clocks;test time reduction
    Date: 1995-01-01
    Issue Date: 2009-11-30 13:15:08 (UTC+8)
    Publisher: Institution of Engineering and Technology (IET)
    Abstract: A postgeneration method for test time reduction of scan-designed circuits is developed. The maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average from given test sets. Further evaluation shows that, for parity scan, the test clocks required by the authors' method are only 41% of those elsewhere.
    Relation: IEE proceedings. Computers and Digital Techniques 142(1), pp.41-48
    DOI: 10.1049/ip-cdt:19951520
    Appears in Collections:[Graduate Institute & Department of Information Management] Journal Article

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