Test set compaction for combinational circuits

淡江大學機構典藏 > 商管學院 > 資訊管理學系暨研究所 > 期刊論文 > Item 987654321/21030

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/21030

题名:	Test set compaction for combinational circuits
作者:	張昭憲;Chang, Jau-shien;Lin, Chen-shang
贡献者:	淡江大學資訊管理學系
关键词:	automatic testing;combinational circuits;integrated circuit testing;logic testing
日期:	1995-11-01
上传时间:	2009-11-30 13:10:57 (UTC+8)
出版者:	New York: Institute of Electrical and Electronics Engineers (IEEE)
摘要:	Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST.
關聯:	IEEE transactions on computer-aided design of integrated circuits and systems 14(11), pp.1370-1378
DOI:	10.1109/43.469663
显示于类别:	[資訊管理學系暨研究所] 期刊論文

文件中的档案:

档案	描述	大小	格式	浏览次数
0278-0070_14(11)p1370-1378.pdf		1053Kb	Adobe PDF	1173	检视/开启
Test set compaction for combinational circuits.pdf		1051Kb	Adobe PDF	1	检视/开启

在機構典藏中所有的数据项都受到原著作权保护.

TAIR相关文章