English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 59063/92570 (64%)
造访人次 : 732599      在线人数 : 51
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻

    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/21030

    题名: Test set compaction for combinational circuits
    作者: 張昭憲;Chang, Jau-shien;Lin, Chen-shang
    贡献者: 淡江大學資訊管理學系
    关键词: automatic testing;combinational circuits;integrated circuit testing;logic testing
    日期: 1995-11-01
    上传时间: 2009-11-30 13:10:57 (UTC+8)
    出版者: New York: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST.
    關聯: IEEE transactions on computer-aided design of integrated circuits and systems 14(11), pp.1370-1378
    DOI: 10.1109/43.469663
    显示于类别:[資訊管理學系暨研究所] 期刊論文


    档案 描述 大小格式浏览次数
    0278-0070_14(11)p1370-1378.pdf1053KbAdobe PDF1106检视/开启
    Test set compaction for combinational circuits.pdf1051KbAdobe PDF0检视/开启



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈