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    題名: Test set compaction for combinational circuits
    作者: 張昭憲;Chang, Jau-shien;Lin, Chen-shang
    貢獻者: 淡江大學資訊管理學系
    關鍵詞: automatic testing;combinational circuits;integrated circuit testing;logic testing
    日期: 1995-11-01
    上傳時間: 2009-11-30 13:10:57 (UTC+8)
    出版者: New York: Institute of Electrical and Electronics Engineers (IEEE)
    摘要: Test set compaction for combinational circuits is studied in this paper. Two active compaction methods based on essential faults are developed to reduce a given test set. The special feature is that the given test set will be adaptively renewed to increase the chance of compaction. In the first method, forced pair-merging, pairs of patterns are merged by modifying their incompatible specified bits without sacrificing the original fault coverage. The other method, essential fault pruning, achieves further compaction from removal of a pattern by modifying other patterns of the test set to detect the essential faults of the target pattern. With these two developed methods, the compacted test size on the ISCAS'85 benchmark circuits is smaller than that of COMPACTEST by more than 20%, and 12% smaller than that by ROTCO+COMPACTEST.
    關聯: IEEE transactions on computer-aided design of integrated circuits and systems 14(11), pp.1370-1378
    DOI: 10.1109/43.469663
    顯示於類別:[資訊管理學系暨研究所] 期刊論文

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