A 5 Gb/s Receiver with Decision Feedback Equalizer and Baud-Rate Clock and Data Recovery Circuit for  8K Displays in 90 nm CMOS Process

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 會議論文 > Item 987654321/126528

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Title:	A 5 Gb/s Receiver with Decision Feedback Equalizer and Baud-Rate Clock and Data Recovery Circuit for 8K Displays in 90 nm CMOS Process
Authors:	Lin, Wei-Ting;Lin, Hung-Yen;Shih, Horng-Yuan
Date:	2024-10-25
Issue Date:	2024-11-26 12:05:19 (UTC+8)
Appears in Collections:	[電機工程學系暨研究所] 會議論文

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