Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/126207

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题名:	Reconfigurable Double-Sampled Cascaded Sigma-Delta Modulator with Power Minimizing and System Stabilizing Strategy for Multi-Mode Applications
作者:	Chen, Hsin Liang;Wang, Chi Hsiung;Chiang, Jen Shiun
关键词:	Cascaded;Reconﬁgurable;Sigma delta modulator;Multi-mode
日期:	2020-12
上传时间:	2024-09-20 12:06:10 (UTC+8)
摘要:	In this paper, a power minimizing strategy from a system- and circuit-perspective is developed for low-power reconfigurable multi-mode sigma-delta modulators. An experimental low-power modulator is designed for multi-mode systems with second- and fourth-order cascaded architectures. Several criteria are obtained to investigate the stability of the cascaded sigma-delta architecture. The proposed modulator can adapt to different system specifications with switchable stages and double-sampled techniques for better power efficiency. A test modulator chip is demonstrated with 0.13 μm CMOS technology. With the proposed strategy, the simulation results indicate that the designed fourth-order cascaded modulator will dissipate powers of 4.2, 11.3, and 20.2 mW and obtain a figure-of-merit (FoM) of 169, 149, and 157 at a supply voltage of 1.2 V for bandwidths 100kHz, 2 MHz, and 20 MHz, respectively.
關聯:	Journal of Applied Science and Engineering, 23(4)
DOI:	10.6180/jase.202012_23(4).0008
显示于类别:	[電機工程學系暨研究所] 期刊論文

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