Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique

淡江大學機構典藏 > 工學院 > 電機工程學系暨研究所 > 期刊論文 > Item 987654321/126203

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题名:	Discrete-Time Delta-Sigma Modulator with Successively Approximating Register ADC Assisted Analog Feedback Technique
作者:	Chen, Hsin-Liang;Chiu, Hong-Ming;Chang, Hung-Chi;Chiang, Jen-Shiun
关键词:	Delta-sigma modulator;Successive approximation register;Analog to digital converter;Sharing digital to analog converter
日期:	2024-09-12
上传时间:	2024-09-20 12:05:51 (UTC+8)
摘要:	This paper proposes a delta-sigma modulator (DSM) for audio band applications with low-area cost and high-resolution performance characteristics. The proposed circuit is implemented by discrete-time switched capacitor circuits. It employs an assisted 6-bit successive approximation register (SAR) analog-to-digital converter (ADC) as the quantizer. Most importantly, it combines and shares the resistive digital-to-analog (DAC) in DSM and SAR ADC. Therefore, it can achieve high-efficiency advantages and reduce the chip layout cost. After all, the chip area is only 0.096 mm2 by the 0.18 um 1P6M CMOS process. It achieves 96 dB dynamic range (DR), 83.1 dB signal to noise and distortion ratio (SNDR), and 93.4 dB signal to noise ratio (SNR) with 25 kHz signal bandwidth and oversampling ratio (OSR) of 64. This is a preview of subscription
關聯:	Circuits System Signal Process
DOI:	10.1007/s00034-024-02832-w
显示于类别:	[電機工程學系暨研究所] 期刊論文

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