The design proposes a low-dropout regulator incorporating dynamic loop gain control to accommodate a wide load current range. It introduces a multi-phase error detection mechanism, a tri-state damping selector, and a dynamic integration shift register. These elements predict load variations and dynamically increase loop gain when the load variation is significant, all without increasing the input clock. This approach achieves a fast response and low power consumption simultaneously. The chip was implemented in 0.18 μm CMOS, with an input operating voltage of 1.2 V and an output voltage of 1 V. The measured results revealed that it could provide output currents from 0.5 to 150 mA, indicating that it had a 300 times wider current range. The maximum current efficiency was 99.93%, and the core area was 0.198 mm2.
