This paper presents advanced data collection methods using boundary scan based vector analysis, developed to debug manufacturing defects on cell based IC's such as JTAG compliant dice. Advantageously, they provide solutions to unknown dice by arranging identically designed Multi-chip Modules (MCM), to thereby diagnose possible flaws on dice due to thermal stresses on substrates as well as cold or hot soldering of the bumps, of which introducing fatigue and cracks, etc., defectives, and this system potentially to repair the problematic MCMs after trouble-shooting the twin-MCMs through self and mutual testing to validate the Known Good Dice (KGD).
