淡江大學機構典藏:Item 987654321/119000
English  |  正體中文  |  简体中文  |  Items with full text/Total items : 58323/91876 (63%)
Visitors : 14059586      Online Users : 99
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
Scope Tips:
  • please add "double quotation mark" for query phrases to get precise results
  • please goto advance search for comprehansive author search
  • Adv. Search
    HomeLoginUploadHelpAboutAdminister Goto mobile version
    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/119000


    Title: Reinforcing the energy efficiency of cyber-physical systems via direct and split cache consolidation on MLC STT-RAM
    Authors: Chen, Shuo-Han;Liang, Yu-Pei;Chang, Yuan-Hao;Liu, Yun-Fei;Wu, Chun-Feng;Wei, Hsin-Wen;Shih, Wei-Kuan
    Keywords: cyber-physical systems;STT-RAM;MLC STT-RAM;direct mapping;cell split mapping
    Date: 2020-03
    Issue Date: 2020-07-28 12:10:51 (UTC+8)
    Abstract: Energy efficiency has become one of the primary considerations in the designs of cyber-physical systems (CPS). However, CPS with static RAM (SRAM)-based processors suffers from the high leakage power issue of SRAM, thus limiting the energy efficiency of CPS. Recently, Spin-Transfer Torque RAM (STT-RAM) has emerged and been widely regarded as a great alternative as the on-chip memory within processors, owing to STT-RAM's high density and near-zero leakage power characteristics. In addition, recent advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to further enhance the memory density. Nevertheless, the write disturbance issue greatly limits the energy efficiency of MLC STT-RAM. Even though studies have been proposed to alleviate this issue, most of the previous disturbance reduction strategies could induce additional management overhead by utilizing counters or cause frequent swap operations when the write disturbance happens. Such observations motivate us to propose a simple and effective solution to unify the direct and split mapping cache designs for improving the energy efficiency of MLC STT-RAM. The proposed design is evaluated through a series of experiments on an emulator with encouraging results.
    Relation: SAC '20: Proceedings of the 35th Annual ACM Symposium on Applied Computing, p.202–209
    DOI: 10.1145/3341105.3373849
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Proceeding

    Files in This Item:

    File Description SizeFormat
    index.html0KbHTML34View/Open

    All items in 機構典藏 are protected by copyright, with all rights reserved.


    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - Feedback