Energy efficiency has become one of the primary considerations in the designs of cyber-physical systems (CPS). However, CPS with static RAM (SRAM)-based processors suffers from the high leakage power issue of SRAM, thus limiting the energy efficiency of CPS. Recently, Spin-Transfer Torque RAM (STT-RAM) has emerged and been widely regarded as a great alternative as the on-chip memory within processors, owing to STT-RAM's high density and near-zero leakage power characteristics. In addition, recent advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to further enhance the memory density. Nevertheless, the write disturbance issue greatly limits the energy efficiency of MLC STT-RAM. Even though studies have been proposed to alleviate this issue, most of the previous disturbance reduction strategies could induce additional management overhead by utilizing counters or cause frequent swap operations when the write disturbance happens. Such observations motivate us to propose a simple and effective solution to unify the direct and split mapping cache designs for improving the energy efficiency of MLC STT-RAM. The proposed design is evaluated through a series of experiments on an emulator with encouraging results.
SAC '20: Proceedings of the 35th Annual ACM Symposium on Applied Computing, p.202–209