A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications

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題名:	A fast-locking all-digital PLL with dynamic loop gain control and phase self-alignment mechanism for sub-GHz IoT applications
作者:	Wei-Bin Yang;Hsi-Hua Wang;Hsin-I Chang;Yu-Lung Lo
日期:	2020-03-06
上傳時間:	2020-07-16 12:10:32 (UTC+8)
出版者:	Institute of Physics Publishing Ltd.
摘要:	This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop gain control and a phase self-alignment mechanism. Compared with conventional fast-locking ADPLLs, the ADPLL proposed in this paper features the phase self-alignment mechanism to resolve overdamping caused by a large KI. Therefore, the proposed ADPLL not only reduces locking time but also maintains jitter performance. In this paper, we used a 0.18 μm standard CMOS process with a supply voltage of 1.8 V. The experimental results indicated that the proposed ADPLL can reduce locking time by 91%. The output frequency range of the proposed ADPLL is 0.7–1 GHz, which is suitable for sub-GHz Internet of Things band applications. At 1 GHz, the power consumption was 10.93 mW, peak-to-peak jitter was 19.53 ps, locking time was 3.5 μs which is 35 TREF, and core area was 0.291 mm2.
關聯:	Japanese Journal of Applied Physics 59(SG), SGGL08
DOI:	10.35848/1347-4065/ab7276
顯示於類別:	[電機工程學系暨研究所] 期刊論文

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