Mitigating write amplification issue of SMR drives via the design of sequential-write-constrained cache

doi:10.1016/j.sysarc.2019.101634

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Title:	Mitigating write amplification issue of SMR drives via the design of sequential-write-constrained cache
Authors:	Yu-Pei Liang, Shuo-Han Chen, Yuan-Hao Chang, Yong-Chin Lin, Hsin-Wen Wei, Wei-Kuan Shih
Keywords:	Sequential-write-constrained cache;SMR drives;Write amplification
Date:	2019-10
Issue Date:	2020-03-07 12:11:03 (UTC+8)
Abstract:	Shingled magnetic recording (SMR) is widely considered as a promising storage technology for fulfilling the capacity requirement of next-generation big data applications. However, owing to the sequential-write constraint imposed by the shingled track layout of SMR drives, random-write requests can only be achieved through read-merge-write operations, which lead to considerable write amplification. An on-disk persistent cache area is used in SMR drives to absorb the random-write requests. However, because of the inherent sequential-write constraint, the on-disk persistent cache area cannot absorb duplicate write traffic through in-place overwriting. Such observation motivates us to propose a sequential-write-constrained cache (SWC2) management to mitigate the write amplification issue of SMR drives with the cached data hotness consideration. The proposed strategy is implemented within the Linux system and the experimental results showed that the overall write latency and cache cleaning latency is reduced by an average of 23.47% and 51.67%, respectively.
Relation:	Journal of Systems Architecture: Embedded Software Design 99
DOI:	10.1016/j.sysarc.2019.101634
Appears in Collections:	[Graduate Institute & Department of Electrical Engineering] Journal Article

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