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    Please use this identifier to cite or link to this item: http://tkuir.lib.tku.edu.tw:8080/dspace/handle/987654321/118162

    Title: A Partial Page Cache Strategy for NVRAM-Based Storage Devices
    Authors: Shuo-Han Chen;Tseng-Yi Chen;Yuan-Hao Chang;Hsin-Wen Wei;Wei-Kuan Shih
    Keywords: Random access memory;Nonvolatile memory;Memory management;Performance evaluation;Embedded systems;Phase change materials
    Date: 2020-02
    Issue Date: 2020-03-05 12:10:38 (UTC+8)
    Publisher: Institute of Electrical and Electronics Engineers
    Abstract: Nonvolatile random access memory (NVRAM) is becoming a popular alternative as the memory and storage medium in battery-powered embedded systems because of its fast read/write performance, byte-addressability, and nonvolatility. A well-known example is phase-change memory (PCM) that has much longer life expectancy and faster access performance than NAND flash. When NVRAM is considered as both main memory and storage in battery-powered embedded systems, existing page cache mechanisms have too many unnecessary data movements between main memory and storage. To tackle this issue, we propose the concept of “union page cache,” to jointly manage data of the page cache in both main memory and storage. To realize this concept, we design a partial page cache strategy that considers both main memory and storage as its management space. This strategy can eliminate unnecessary data movements between main memory and storage without sacrificing the data integrity of file systems. A series of experiments was conducted on an embedded platform. The results show that the proposed strategy can improve the file accessing performance up to 85.62% when PCM used as a case study.
    Relation: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39(2), p.373-386
    DOI: 10.1109/TCAD.2018.2887045
    Appears in Collections:[Graduate Institute & Department of Electrical Engineering] Journal Article

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