English  |  正體中文  |  简体中文  |  全文筆數/總筆數 : 62570/95233 (66%)
造訪人次 : 2550307      線上人數 : 130
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜尋範圍 查詢小技巧:
  • 您可在西文檢索詞彙前後加上"雙引號",以獲取較精準的檢索結果
  • 若欲以作者姓名搜尋,建議至進階搜尋限定作者欄位,可獲得較完整資料
  • 進階搜尋
    請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/117344

    題名: FPGA-based hardware design for scale-invariant feature transform
    作者: 李世安
    關鍵詞: Hardware;Computer architecture;Field programmable gate arrays;Feature extraction;Computational efficiency;Real-time systems;Transforms
    日期: 2018-08-03
    上傳時間: 2019-10-08 12:10:36 (UTC+8)
    出版者: IEEE
    摘要: This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.
    關聯: IEEE Access
    顯示於類別:[電機工程學系暨研究所] 專書


    檔案 描述 大小格式瀏覽次數
    FPGA-based hardware design for scale-invariant feature transform.pdf318KbAdobe PDF101檢視/開啟



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回饋