English  |  正體中文  |  简体中文  |  全文笔数/总笔数 : 62567/95223 (66%)
造访人次 : 2524270      在线人数 : 38
RC Version 7.0 © Powered By DSPACE, MIT. Enhanced by NTU Library & TKU Library IR team.
搜寻范围 查询小技巧:
  • 您可在西文检索词汇前后加上"双引号",以获取较精准的检索结果
  • 若欲以作者姓名搜寻,建议至进阶搜寻限定作者字段,可获得较完整数据
  • 进阶搜寻

    jsp.display-item.identifier=請使用永久網址來引用或連結此文件: https://tkuir.lib.tku.edu.tw/dspace/handle/987654321/117023

    题名: FPGA-based hardware design for scale-invariant feature transform
    关键词: Hardware;Computer architecture;Field programmable gate arrays;Feature extraction;Computational efficiency;Real-time systems;Transforms
    日期: 2018-08-03
    上传时间: 2019-09-17 12:12:09 (UTC+8)
    出版者: IEEE
    摘要: This paper proposes a novel hardware design method of scale-invariant feature transform (SIFT) algorithm for implementation on field-programmable gate array (FPGA). To reduce the computing costs, Gaussian kernels are calculated offline for use in Gaussian filters. To eliminate low-contrast points, the inverse of a Hessian matrix is required for hardware implementation, which results in poor performance because dividers are needed. To solve this problem, this paper presents a new mathematical derivation model to implement the low-contrast detection, avoiding the use of any dividers. For the implementation of the normalization module, a large number of dividers are required by traditional methods, which adversely affects the computational efficiency. This paper presents a new architecture using only one divider to implement the normalization function in hardware. Thanks to the parallel processing architecture proposed to design the image pyramid, SIFT detection, and SIFT descriptor, the computational efficiency of the SIFT algorithm is significantly improved. As a result of the proposed design method, the requirement of logic elements in the FPGA hardware is greatly reduced and system frequency is significantly increased. Experimental results show that the proposed hardware architecture outperforms existing techniques in terms of resource usage and computational efficiency for real-time image processing.
    關聯: IEEE Access 6, p.43850-43864
    DOI: 10.1109/ACCESS.2018.2863019
    显示于类别:[電機工程學系暨研究所] 期刊論文


    档案 描述 大小格式浏览次数
    FPGA-based hardware design for scale-invariant feature transform.pdf318KbAdobe PDF66检视/开启



    DSpace Software Copyright © 2002-2004  MIT &  Hewlett-Packard  /   Enhanced by   NTU Library & TKU Library IR teams. Copyright ©   - 回馈